Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A PRML system with a branch estimator. The PRML system includes an analog-to-digital converter (ADC) for receiving an analog input signal and converting the analog input signal into a digital sampled signal according a sampling clock; a branch estimator for receiving the digital sampled signal and estimating each branch eigenvalue; and a Viterbi decoder for decoding an output signal according to the digital sampled signal and the branch eigenvalues. Since the PRML system employs the branch estimator to estimate the branch eigenvalues of trellis of the Viterbi decoder directly, the PRML system can be simplified and the execution speed of the PRML system can be increased.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A survivor path memory circuit and a Viterbi decoder with the circuit for saving the memory amounts. The Viterbi decoder includes a branch metric generator, an ACS (Add-Compare-Select) unit, a survivor path memory circuit and a decoding unit. The survivor path memory circuit includes survivor paths and decision bit paths. Each survivor path has multiplexers connected in series and each multiplexer outputs the selected data to next multiplexer and to another multiplexers of another survivor paths. Each decision bit path has register node connected in series, receives a decision bit signal generated from the ACS unit, and outputs delayed signal to the multiplexers of the corresponding survivor path. The data flow direction for the survivor paths is opposite to the data flow direction for the decision bit paths.

Abstract: A survivor path memory circuit and a Viterbi decoder with the circuit for saving the memory amounts. The Viterbi decoder includes a branch metric generator, an ACS (Add-Compare-Select) unit, a survivor path memory circuit and a decoding unit. The survivor path memory circuit includes survivor paths and decision bit paths. Each survivor path has multiplexers connected in series and each multiplexer outputs the selected data to next multiplexer and to another multiplexers of another survivor paths. Each decision bit path has register node connected in series, receives a decision bit signal generated from the ACS unit, and outputs delayed signal to the multiplexers of the corresponding survivor path. The data flow directions for the survivor paths and decision bit paths are in reverse direction.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A PRML system with a branch estimator. The PRML system includes an analog-to-digital converter (ADC) for receiving an analog input signal and converting the analog input signal into a digital sampled signal according a sampling clock; a branch estimator for receiving the digital sampled signal and estimating each branch eigenvalue; and a Viterbi decoder for decoding an output signal according to the digital sampled signal and the branch eigenvalues. Since the PRML system employs the branch estimator to estimate the branch eigenvalues of trellis of the Viterbi decoder directly, the PRML system can be simplified and the execution speed of the PRML system can be increased.

Abstract: A modified three-pixel antialiasing method wherein the closest pixel from a displayed line has a constant display intensity includes the steps of locating a first pixel having a shortest distance along an axis of the pixel matrix array from the line, determining the shortest distance, calculating pixel intensity for the first pixel by multiplying a maximum intensity of the first pixel with a constant value, locating a second pixel having a second shortest distance along the axis from the line, locating a third pixel having a third shortest distance along the axis from the line, calculating pixel intensity for the second pixel, and calculating pixel intensity for the third pixel.

Abstract: A multiplication device is provided for forming the product of a first and a second N-bit input binary number. The multiplication device receives the two input binary numbers and forms a two's complement product expressed in a product sum and a product carry term. The product sum and product carry terms are formed by providing an offset generation means which generates a numerical binary offset of the value determined by X=(4-2.sup.-(n-1)) and a partial product generating means which generates first and second sets of partial products. An addition means adds the offset value and first and second sets of partial products are added to form the resultant product sum and product carry terms. The product sum and product carry terms are conveyed to a second addition means wherein they are added to form a two's complement product result. Preferably the multiplication device is provided with an accumulation means to form the sum of the products of all successive pairs of input binary numbers.