Abstract: A PRML system with a branch estimator. The PRML system includes an analog-to-digital converter (ADC) for receiving an analog input signal and converting the analog input signal into a digital sampled signal according a sampling clock; a branch estimator for receiving the digital sampled signal and estimating each branch eigenvalue; and a Viterbi decoder for decoding an output signal according to the digital sampled signal and the branch eigenvalues. Since the PRML system employs the branch estimator to estimate the branch eigenvalues of trellis of the Viterbi decoder directly, the PRML system can be simplified and the execution speed of the PRML system can be increased.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A survivor path memory circuit and a Viterbi decoder with the circuit for saving the memory amounts. The Viterbi decoder includes a branch metric generator, an ACS (Add-Compare-Select) unit, a survivor path memory circuit and a decoding unit. The survivor path memory circuit includes survivor paths and decision bit paths. Each survivor path has multiplexers connected in series and each multiplexer outputs the selected data to next multiplexer and to another multiplexers of another survivor paths. Each decision bit path has register node connected in series, receives a decision bit signal generated from the ACS unit, and outputs delayed signal to the multiplexers of the corresponding survivor path. The data flow direction for the survivor paths is opposite to the data flow direction for the decision bit paths.