Patents by Inventor Wendell P. Noble, Jr.
Wendell P. Noble, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7105386Abstract: High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: March 9, 2004Date of Patent: September 12, 2006Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6964903Abstract: A method provides a structure that includes dual-gated metal-oxide semiconducting field effect transistor (MOSFET). The dual-gated MOSFET can be fabricated according to current CMOS processing techniques. The method includes forming a body region of the dual-gated MOSFET as a fully depleted structure. The structure includes two gates which are positioned on opposite sides of the opposing sides of the body region. Further, the structure operates as one device where the threshold voltage of one gate depends on the bias of the other gate. Thus, the structure yields a small signal component in analog circuit applications which depends on the product of the signals applied to the gates, and not simply one which depends on the sum of the two signals.Type: GrantFiled: January 25, 2002Date of Patent: November 15, 2005Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Wendell P. Noble, Jr.
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Patent number: 6936886Abstract: High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: December 29, 2000Date of Patent: August 30, 2005Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6773968Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.Type: GrantFiled: July 3, 2000Date of Patent: August 10, 2004Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Wendell P. Noble, Jr.
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Patent number: 6545297Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: May 13, 1998Date of Patent: April 8, 2003Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6503790Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: June 4, 2001Date of Patent: January 7, 2003Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6420748Abstract: It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material.Type: GrantFiled: September 8, 2000Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Mark C. Hakey, David V. Horak, William H. Ma, Wendell P. Noble, Jr.
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Patent number: 6271555Abstract: A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline.Type: GrantFiled: March 31, 1998Date of Patent: August 7, 2001Assignee: International Business Machines CorporationInventors: Mark C. Hakey, Steven J. Holmes, David V. Horak, Wendell P. Noble, Jr.
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Patent number: 6261933Abstract: It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the wordline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material.Type: GrantFiled: January 31, 2000Date of Patent: July 17, 2001Assignee: International Business Machines CorporationInventors: Mark C. Hakey, David V. Horak, William H. Ma, Wendell P. Noble, Jr.
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Patent number: 6252267Abstract: The present invention is a DRAM cell, comprising a transistor having a gate, the gate having an individual segment of gate conductor and a conductive spacer rail wordline in contact with the segment gate. The wordline connector is formed by directional etching a conductor formed along a sidewall above the gate segment. The sidewall is formed by etching a groove in a mandrel. The structure permits design of a five square folded-bitline DRAM cell.Type: GrantFiled: December 28, 1994Date of Patent: June 26, 2001Assignee: International Business Machines CorporationInventor: Wendell P. Noble, Jr.
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Patent number: 6225165Abstract: High density static memory cells and arrays containing gated lateral bipolar transistors which can be latched in a bistable on state. Each transistor memory cell includes two gates which are pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.Type: GrantFiled: May 13, 1998Date of Patent: May 1, 2001Assignee: Micron Technology, Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6175128Abstract: It is a feature of the present invention that a subminimum dimension wordline links approximately minimum dimensional individual gate segments with the bitline contact being borderless to the worldline. It is still a further object of the present invention to provide a transistor with an individual segment gate conductor and a subminimum dimension gate connector with the bitline contact being borderless to the wordline. A semiconductor structure and method of making same comprising a DRAM cell which has a transistor which includes a gate. The gate comprises an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further comprises a single crystal semiconductor substrate having a source/drain region. An active conductive wordline is deposited on top of and electrically contacting the segment gate conductor with the wordline being a conductive material.Type: GrantFiled: March 31, 1998Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Mark C. Hakey, David V. Horak, William H. Ma, Wendell P. Noble, Jr.
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Patent number: 6128216Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes gates which are pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.Type: GrantFiled: May 13, 1998Date of Patent: October 3, 2000Assignee: Micron Technology Inc.Inventors: Wendell P. Noble, Jr., Leonard Forbes
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Patent number: 6121128Abstract: A semiconductor structure and method of making the same are disclosed which includes a DRAM cell which has a transistor which includes a gate. The gate includes an individual segment of gate conductor such as polysilicon on a thin dielectric material. The transistor further has a single crystal semiconductor substrate having a source/drain region. An active conducting wordline is deposited on top of and electrically contacting a segment gate conductor, the wordline being a conductive material having a top and sidewalls. Electrically insulating material completely surrounds the active wordline except where the active wordline contacts the segment gate conductor. The insulating material surrounding the active wordline includes silicon nitride overlying the top and surrounding a portion of the sidewalls thereof, and silicon dioxide surrounds the remainder of the side walls of the active wordline.Type: GrantFiled: September 17, 1999Date of Patent: September 19, 2000Assignee: International Business Machines CorporationInventors: Mark C. Hakey, Steven J. Holmes, David V. Horak, Wendell P. Noble, Jr.
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Patent number: 6104045Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.Type: GrantFiled: May 13, 1998Date of Patent: August 15, 2000Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Wendell P. Noble, Jr.
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Patent number: 6090660Abstract: The present invention is a DRAM cell, comprising a transistor having a gate, the gate having an individual segment of gate conductor and a conductive spacer rail wordline in contact with the segment gate. The wordline connector is formed by directional etching a conductor formed along a sidewall above the gate segment. The sidewall is formed by etching a groove in a mandrel. The structure permits design of a five square folded-bitline DRAM cell.Type: GrantFiled: October 18, 1995Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventor: Wendell P. Noble, Jr.
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Patent number: 6022781Abstract: A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.Type: GrantFiled: December 23, 1996Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Wendell P. Noble, Jr., Ashwin K. Ghatalia, Badih El-Kareh
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Patent number: 5539229Abstract: A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.Type: GrantFiled: December 28, 1994Date of Patent: July 23, 1996Assignee: International Business Machines CorporationInventors: Wendell P. Noble, Jr, Ashwin K. Ghatalia, Badih El-Kareh
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Patent number: 5512767Abstract: Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.Type: GrantFiled: December 13, 1994Date of Patent: April 30, 1996Assignee: International Business Machines Corp.Inventor: Wendell P. Noble, Jr.
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Patent number: 5422294Abstract: Structures and methods are presented for forming a field shield for a trench capacitor for a memory cell with a contact through insulator along a sidewall of the trench to a desired region of the semiconducting substrate. The desired region is typically held at a substantially fixed potential; in any case it does not include a node diffusion.Type: GrantFiled: May 3, 1993Date of Patent: June 6, 1995Inventor: Wendell P. Noble, Jr.