Patents by Inventor Wen Feng Wu

Wen Feng Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143045
    Abstract: An independent graphics card system comprises an expansion motherboard, a system power supply, at least one expansion graphics card and a fan assembly. The system power supply is electrically connected to the expansion motherboard. The at least one expansion graphics card is plugged into the expansion motherboard through an adapter card. The at least one expansion graphics card is parallel with the expansion motherboard. The fan assembly dissipates heat of the at least one expansion graphics card.
    Type: Application
    Filed: October 18, 2023
    Publication date: May 2, 2024
    Inventors: SUNG-HSIEN LEE, WEN-KE WU, ZHI-FENG WEI, BIAO ZENG
  • Publication number: 20240101784
    Abstract: A novel additive for recycling thermoset materials, its related recyclable thermoset composition and its application are disclosed. Specifically, the composition of the additive comprises at least one copolymer that has at least one carbamate group, at least one carbonate group and/or at least one urea group, and a number-average molecular weight of the copolymer is between 100 and 50,000 Da.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 28, 2024
    Inventors: Chien-Hsin Wu, Ying-Chi Huang, Ying-Feng Lin, Wen-Chang Chen, Ho-Ching Huang, Ru-Jong Jeng
  • Publication number: 20240096848
    Abstract: A method of manufacturing a semiconductor device includes forming a first bonding layer over a substrate of a first wafer, the first wafer including a first semiconductor die and a second semiconductor die, performing a first dicing process to form two grooves that extend through the first bonding layer, the two grooves being disposed between the first semiconductor die and the second semiconductor die, performing a second dicing process to form a trench that extends through the first bonding layer and partially through the substrate of the first wafer, where the trench is disposed between the two grooves, and thinning a backside of the substrate of the first wafer until the first semiconductor die is singulated from the second semiconductor die.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 21, 2024
    Inventors: Chih-Wei Wu, Ching-Feng Yang, Ying-Ching Shih, An-Jhih Su, Wen-Chih Chiou
  • Publication number: 20240071911
    Abstract: A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
    Type: Application
    Filed: January 31, 2023
    Publication date: February 29, 2024
    Inventors: Harry-Haklay Chuang, Wen-Tuo Huang, Li-Feng Teng, Wei-Cheng Wu, Yu-Jen Wang
  • Patent number: 7882621
    Abstract: A method for making chip resistor components includes: (a) forming a plurality of first and second notches in a substrate so as to form resistor-forming strips; (b) forming pairs of upper and lower electrodes on each of the resistor-forming strips; (c) forming a resistor film on each of the resistor-forming strips; (d) forming an insulator layer on the resistor film; (e) forming a hole pattern in the insulator layer and the resistor film; (f) forming an insulating shield layer on the insulator layer; (g) cleaving the substrate along the first notches so as to form a plurality of strip-like semi-finished products; (h) forming a pair of side electrodes on two opposite sides of each of the semi-finished products; and (i) cleaving each of the semi-finished products.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 8, 2011
    Assignee: Yageo Corporation
    Inventors: Mu-Yuan Chen, Wen-Feng Wu, Chi-Pin Chang, Kao-Po Chien
  • Publication number: 20090217511
    Abstract: A method for making chip resistor components includes: (a) forming a plurality of first and second notches in a substrate so as to form resistor-forming strips; (b) forming pairs of upper and lower electrodes on each of the resistor-forming strips; (c) forming a resistor film on each of the resistor-forming strips; (d) forming an insulator layer on the resistor film; (e) forming a hole pattern in the insulator layer and the resistor film; (f) forming an insulating shield layer on the insulator layer; (g) cleaving the substrate along the first notches so as to form a plurality of strip-like semi-finished products; (h) forming a pair of side electrodes on two opposite sides of each of the semi-finished products; and (i) cleaving each of the semi-finished products.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 3, 2009
    Applicant: YAGEO CORPORATION
    Inventors: Mu-Yuan Chen, Wen-Feng Wu, Chi-Pin Chang, Kao-Po Chien
  • Patent number: 6480794
    Abstract: To allocate products for machines on a manufacturing line, provide a standard test time. Minimize total test time with respect to production scheduling. Form a supply demand matrix table for products and machines for product allocation. Find the grid location with minimum testing time. Provide maximum time allocation from a machine at the corresponding position on the matrix table. Determine the grid location with the next minimum testing time. Loop back to provide a maximum allocation of remaining time from the corresponding machine and repeat looping back until no demand is left. Find need for an optimum testing process by testing whether only one machine can test the product and no quantity is allocated to a machine. If YES branch to calculate utilization per machine. If NO, decide whether NCOL+NLIN−1=NVB. If YES perform optimum testing. If NO, branch to calculate machine utilization per machine.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: November 12, 2002
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Hsiu Hsieh, Fu-Kang Lai, Wen-Feng Wu, Yi-Hsin Chan, Yao-Tung Liu, Yi-Chin Hsu
  • Patent number: 6356797
    Abstract: A method for automatic scheduling of a production plan. The automatic scheduling system arranges different kinds of production plans and defines a first priority lot, a second priority lot and a normal lot in testing factories. The testing processes of the first priority lot is to decide the testing machine first, then exchanged with a running lot on this testing machine when a test piece is completed. For the second priority lot, after decides the testing machine, the second priority lot is exchanged with a running lot on the testing machine when the running lot is completed. For the normal lot, the procedure is to check if the testing machine is available and need to be setup, then use a setup reduce method to reduce the setup frequency if more than one machine is available and needs to be setup. The key to reduce setup method selects the testing machine which has minimum impact for the subsequent testing lot to get efficient use of the testing machine.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: March 12, 2002
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsiu Hsieh, Wen-Feng Wu, Min-Huey Tsai, Yao-Tung Liu, Lieh-Chang Tai
  • Patent number: 6256550
    Abstract: A manufacturing control and reporting method/system for manufacture of semiconductor devices comprises a system for loading a mechanical article handling device in a semiconductor manufacturing system, provides an automatic check-in and changing equipment status to an UP status, automatically checking whether the article handling system is empty, and for automatically changing the system status to an IDLE status. The system provides automatic check-in, and subsequent to processing of the workload by the plant provides track-out followed by automatically checking whether the article handling system is empty. Then the system checking whether a TE has arrived, and the system checks whether the TE has reloaded the article handling system.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: July 3, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Wen Feng Wu, Ming-Hsiu Hsieh, Pai-Lan Chen, Ching-Ren Chen, Hui-Ping Liu