Patents by Inventor Weng Hong Teh
Weng Hong Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021562Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: Weng Hong TEH, Chia-Pin CHIU
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Publication number: 20230420400Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Pramod MALATKAR, Weng Hong TEH, John S. GUZEK, Robert L. SANKMAN
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Patent number: 11810884Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: GrantFiled: January 6, 2022Date of Patent: November 7, 2023Assignee: Intel CorporationInventors: Weng Hong Teh, Chia-Pin Chiu
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Publication number: 20220130789Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Inventors: Weng Hong TEH, Chia-Pin CHIU
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Publication number: 20220068861Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Inventors: Pramod MALATKAR, Weng Hong TEH, John S. GUZEK, Robert L. SANKMAN
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Patent number: 11264301Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: March 17, 2020Date of Patent: March 1, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Patent number: 11251150Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: GrantFiled: October 22, 2020Date of Patent: February 15, 2022Assignee: Intel CorporationInventors: Weng Hong Teh, Chia-Pin Chiu
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Patent number: 11201128Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.Type: GrantFiled: December 23, 2015Date of Patent: December 14, 2021Assignee: Intel CorporationInventors: Pramod Malatkar, Weng Hong Teh, John S. Guzek, Robert L. Sankman
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Patent number: 11094604Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: June 27, 2019Date of Patent: August 17, 2021Assignee: Western Digital Technologies, Inc.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Publication number: 20210043596Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: ApplicationFiled: October 22, 2020Publication date: February 11, 2021Inventors: Weng Hong TEH, Chia-Pin CHIU
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Patent number: 10861815Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: GrantFiled: September 5, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Weng Hong Teh, Chia-Pin Chiu
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Publication number: 20200219787Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: March 17, 2020Publication date: July 9, 2020Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
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Patent number: 10636722Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: GrantFiled: September 26, 2017Date of Patent: April 28, 2020Assignee: Western Digital Technologies, Inc.Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh
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Patent number: 10636769Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.Type: GrantFiled: September 10, 2018Date of Patent: April 28, 2020Assignee: Intel CorporationInventors: Weng Hong Teh, John S. Guzek, Shan Zhong
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Publication number: 20190393180Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: ApplicationFiled: September 5, 2019Publication date: December 26, 2019Inventors: Weng Hong Teh, Chia-Pin Chiu
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Patent number: 10508961Abstract: A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.Type: GrantFiled: November 24, 2015Date of Patent: December 17, 2019Assignee: INTEL CORPORATIONInventors: Kevin L. Lin, Qing Ma, Feras Eid, Johanna Swan, Weng Hong Teh
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Publication number: 20190326194Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: June 27, 2019Publication date: October 24, 2019Inventors: Lee Kong YU, Sungjun IM, Chun Sean LAU, Yoong Tatt CHIN, Paramjeet Singh GILL, Weng-Hong TEH
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Patent number: 10438915Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: GrantFiled: January 4, 2019Date of Patent: October 8, 2019Assignee: Intel CorporationInventors: Weng Hong Teh, Chia-Pin Chiu
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Publication number: 20190139926Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.Type: ApplicationFiled: January 4, 2019Publication date: May 9, 2019Inventors: Weng Hong Teh, Chia-Pin Chiu
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Publication number: 20190096783Abstract: A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.Type: ApplicationFiled: September 26, 2017Publication date: March 28, 2019Inventors: Lee Kong Yu, Sungjun Im, Chun Sean Lau, Yoong Tatt Chin, Paramjeet Singh Gill, Weng-Hong Teh