Patents by Inventor Weng Li Leow
Weng Li Leow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240070039Abstract: The present invention relates to a method of debugging a targeted area or the whole network-on-chip (NOC) (101), whereby said targeted area or the whole NOC is triggered to enter into a freeze state before capturing of the state of the targeted area or the whole NOC (101) and unloading of the debug information, before finally said targeted area or the whole NOC is triggered to enter into an unfreeze state to allow forward progress to resume, using existing buffer storage, thus allowing user to debug and identify the source of issue without requiring a significant amount of extra storage.Type: ApplicationFiled: October 7, 2022Publication date: February 29, 2024Inventors: Yu Ying ONG, Chee Hak TEH, Soon Chieh LIM, Weng Li LEOW, Muhamad Aidil BIN JAZMI, Yeong Tat LIEW
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Patent number: 11829643Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.Type: GrantFiled: December 27, 2021Date of Patent: November 28, 2023Assignee: SKYECHIP SDN BHDInventors: Chee Hak Teh, Yu Ying Ong, Weng Li Leow, Muhamad Aidil Bin Jazmi
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Publication number: 20230129791Abstract: A memory controller system (and method of pre-scheduling memory transaction) for a storage device comprising a linked-list controller; a plurality of command buffers to store read commands or write commands, and an arbiter to issue command. Each command buffer containing variables set by the linked-list controller. The linked-list controller is configured to execute commands in sequence independent of logical command buffer sequence. The command buffer is configured to support read commands with maximum number of write commands. The linked-list controller is configured to merge multiple write commands that are going to the same address and snarfs read commands from write commands if both commands are going to the same address and the read commands that are snarfed are loaded into a separate command buffer. The variables contained in each of the command buffer indicates status and dependency of the command buffer to create a link forming a command sequence.Type: ApplicationFiled: December 27, 2021Publication date: April 27, 2023Applicant: SKYECHIP SDN BHDInventors: Chee Hak TEH, Yu Ying ONG, Weng Li LEOW, Muhamad Aidil Bin JAZMI
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Patent number: 9922693Abstract: The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.Type: GrantFiled: February 1, 2017Date of Patent: March 20, 2018Assignee: Altera CorporationInventors: Kay Keat Khoo, Weng Li Leow
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Publication number: 20170287543Abstract: The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.Type: ApplicationFiled: February 1, 2017Publication date: October 5, 2017Applicant: ALTERA CORPORATIONInventors: Kay Keat KHOO, Weng Li LEOW
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Patent number: 9595312Abstract: The present disclosure provides for adaptive scheduling of memory refreshes. One embodiment relates to a method of adapting an initial refresh sequence. In this method, flow and blockage scores for each refresh sequence of a plurality of refresh sequences are obtained and stored in an array of scores. An initial refresh sequence is selected in a way that favors a high flow score and a low blockage score. Another embodiment relates to a method of adapting a current refresh sequence. Current flow and blockage scores are obtained and stored for the current refresh sequence. The current flow and blockage scores are used to update (by averaging, for example) the existing flow and blockage scores for the current refresh sequence. The next refresh sequence is then chosen from amongst a plurality of refresh sequences in a way that favors a high flow score and a low blockage score.Type: GrantFiled: March 31, 2016Date of Patent: March 14, 2017Assignee: Altera CorporationInventors: Kay Keat Khoo, Weng Li Leow
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Patent number: 9189426Abstract: Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture (“PMMA”) may be configured to control accesses to protected physical memory. The PMMA may provide a protected virtual memory window for dynamic allocation of protected memory regions. During forward translation of virtual memory addresses, the PMMA may check a region ID of a process before allowing access. During reverse translation of a physical memory address, the PMMA may prevent accesses to protected physical memory addresses. The PMMA may also dynamically allocate physical memory to protected memory regions in virtual memory and may authenticate the physical memory as available before allocation. Other embodiments may be described and claimed.Type: GrantFiled: June 28, 2012Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Chee Hak Teh, Weng Li Leow, Alok K. Mathur
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Publication number: 20140006737Abstract: Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture (“PMMA”) may be configured to control accesses to protected physical memory. The PMMA may provide a protected virtual memory window for dynamic allocation of protected memory regions. During forward translation of virtual memory addresses, the PMMA may check a region ID of a process before allowing access. During reverse translation of a physical memory address, the PMMA may prevent accesses to protected physical memory addresses. The PMMA may also dynamically allocate physical memory to protected memory regions in virtual memory and may authenticate the physical memory as available before allocation. Other embodiments may be described and claimed.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Inventors: Chee Hak Teh, Weng Li Leow, Alok K. Mathur