Abstract: A 3D memory device includes a conductor/insulator stack containing a conductive layer and a dielectric layer alternatingly stacked, channel hole structures in a first region of memory cells in the conductor/insulator stack, a blocking structure adjacent to the first region, and a dummy channel hole structure in the first region. The dummy channel hole structure is adjacent to the blocking structure, and includes a dielectric material that fills a channel hole to form a first dielectric filling structure.

Abstract: A federated learning training method is performed by a server. The method comprises: receiving gradient information of a labeled sample of each client sent by each client; according to the gradient information sent by each client, obtaining target gradient information belonging to a same labeled sample; determining a client to which each labeled sample belongs; and sending, to a client to which the same labeled sample belongs, the target gradient information corresponding to the same labeled sample.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the first semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor.

Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a method for forming a 3D memory device can comprise forming a first semiconductor structure, comprising forming a stack structure on a first substrate, and forming a gate line slit structure including a filling structure penetrating the stack structure and extending into the first substrate. The method can further comprise forming a second semiconductor structure including a periphery circuit on a second substrate, and bonding the second semiconductor structure to the first semiconductor structure. The method can further comprise removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate, and forming a supplemental semiconductor layer on a remaining portion of the first substrate.

Abstract: Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device comprises a first semiconductor structure including a core region, a spacer region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure comprises a memory stack on a semiconductor layer in the core region, a first periphery circuit on the semiconductor layer in the periphery region, and a spacer structure in the spacer region to separate the memory stack and the first periphery circuit. The second semiconductor structure is connected to the first semiconductor structure.

Abstract: Aspects of the disclosure provide a semiconductor device including a stack structure and a first conductive pillar. The stack structure can include a plurality of interlayer insulating layers and gate layers arranged alternately along a stack direction, and stack structure an array region and a staircase region adjoining the array region. The stack structure has a plurality of staircases in the staircase region arranged corresponding to the gate layers. Each of the gate layers can include a first gate part at the corresponding staircase and a second gate part connected to the first gate part, and a thickness of the first gate part along the stack direction is less than that of the second gate part along the stack direction. The first conductive pillar is arranged in the staircase region and penetrates through the stack structure along the stack direction, and the first conductive pillar is electrically connected with the first gate part.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, memory cells, a semiconductor layer, a contact structure, and gate line slit structures. The substrate includes a doped region. The layer stack is formed over the substrate. The memory cells are formed through the layer stack over the substrate. The semiconductor layer is formed on the doped region and a side portion of a channel layer that extends through the layer stack. The contact structure electrically contacts the doped region. A dielectric material is filled in the gate line slit structures. Air gaps are formed in the gate line slit structures by the dielectric material.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: In a method for training a federated learning model, a server obtains a target split mode corresponding to a training node in response to determining that the training node satisfies a preset splitting condition. The server notifies a client to perform, based on the target split mode, node splitting. The server performs a next round of training by taking a left subtree node generated by performing the node splitting as a new training node until an updated training node does not satisfy the preset splitting condition. The server performs a next round of training by taking another non-leaf node of the boosting tree as a new training node. The server stops training and generates a target federated learning model in response to determining that a node dataset of the plurality of boosting trees is empty.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.

Abstract: A JAK inhibitor may be used in preparation of a medicament. The medicament may be used for preventing and/or treating a disease or condition associated with an antitumor agent in a subject. A pharmaceutical composition may include the JAK inhibitor as may a kit. The JAK inhibitor may include a compound of formula (I) or a pharmaceutically acceptable salt thereof: Q, X, Y, and Z being independently N or C, and R1, R2 and R3 being independently a 5-6-membered aromatic ring, 5-6-membered heteroaromatic ring, 5-6-membered cycloalkyl, 5-6-membered heterocycloalkyl, amino, or amido, the aromatic ring, heteroaromatic ring, cycloalkyl, and/or heterocycloalkyl being optionally substituted by a substituent.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

Abstract: A method and a device for testing a memory, and a non-transitory readable storage medium are provided. The method for testing the memory includes: executing a memory testing program to perform a memory test on a first area of the memory, the first area being an area that is not occupied by the memory testing program; writing address information of a second area into an external memory of a device, the second area being an area that is occupied by the memory testing program; transferring, after the memory test on the first area is completed, the memory testing program into a partial area of the first area according to the address information of the second area recorded in the external memory; and executing the memory testing program to perform the memory test on the second area.

Abstract: A post package repairing method for a memory includes: during a memory test, writing failure information of the memory into the memory, the failure information including failure addresses; after a device is powered on, reading the failure addresses from the memory, and determining a number of failed lines where the failure addresses are located; when the number of the failed lines is less than or equal to a number of redundant lines, repairing the failed lines by using the redundant lines; and when the number of the failed lines is greater than the number of the redundant lines, loading the failure information into a register.