Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: A cordless telephone which allows a user to play MP3 digital audio bit stream music, a video game, either alone or with a user of another cordless telephone, using the remote handset of a cordless telephone to control the functions of the MP3 player. The cordless telephone remains usable as a typical cordless telephone with all the features and conveniences of a cordless telephone including, but not limited to, connection of a telephone call between a calling party and a called party, caller ID information, voice messaging features, etc. MP3 digital audio bit stream music may be downloaded from a remote source through, e.g., the Internet and a PC.

Abstract: A current switching circuit has greatly reduced charge injection effects with the introduction of a mirror path to mirror the switch path. The mirror path comprises a complementary switch and a pulling amplifier, e.g., a pull-down amplifier for a source current switching circuit, or a pull-up amplifier for a sink current switch circuit. The pulling amplifier mirrors the status of an output path of a current source, e.g., a transistor current source, such that when the current source is switched ON or OFF, the switching process with respect to the load, e.g., a load capacitor, is smooth and provides a clean current waveform due to greatly reduced charge injection.

Abstract: The present invention relates to a new feature for e-mail services which provides a telephone call alert to a particular e-mail user when their e-mail server, web page e-mail server, or other e-mail receiving server receives new e-mail addressed to them. One or more designated telephone number (or numbers) are automatically called by an auto dialer at the e-mail server in response to the receipt of particularly identified high priority e-mail senders (e.g., from clients, from family, etc.). The particular designated telephone number(s) to call for a particular user are configured in a priority alert profile for that particular user, as are the possibility to limit the activation of the telephone call alert system to electronic messages received only from a select list of senders, and/or after a predetermined number of electronic messages have been received.

Abstract: The present invention relates to a new feature for e-mail services which provides a telephone call alert to a particular e-mail user when their e-mail server, web page e-mail server, or other e-mail receiving server receives new e-mail addressed to them. One or more designated telephone number (or numbers) are automatically called by an auto dialer at the e-mail server in response to the receipt of particularly identified high priority e-mail senders (e.g., from clients, from family, etc.). The particular designated telephone number(s) to call for a particular user are configured in a priority alert profile for that particular user, as are the possibility to limit the activation of the telephone call alert system to electronic messages received only from a select list of senders, and/or after a predetermined number of electronic messages have been received.

Abstract: An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.

Abstract: A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Abstract: An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.

Abstract: The present invention provides a baseband RF clock synthesizer having particular use in a BLUETOOTH piconet device, which has the capability of providing simple and accurate calibration of modulation path gain (KMOD) by introducing a dual-loop phase locked loop (PLL) in the RF clock signal synthesizer. The disclosed technique and apparatus controls the maximum frequency deviation by the difference of two locked frequencies, one frequency in each path of the dual-path PLL. Once the PLL is locked within some frequency error, the present technique and apparatus calibrates for the deviation of amplitude of the modulation due to the modulation path. Accordingly, modulation gain (KMOD) calibration is provided by adding an auxiliary loop to a PLL in an RF frequency synthesizer.

Abstract: A data-pattern feedback mechanism is introduced into the peak detection process of an automatic frequency compensation system in a Gaussian Frequency Shift Keying (GFSK) modulated system, providing fast and accurate fine-stage automatic frequency compensation (AFC). Maximum positive and negative peak registers are updated with new values as necessary based on detection during a sequence of identical binary bit values (e.g., during a “00” for detection of maximum negative peak frequency, or during a “11” for detection of maximum positive peak frequency), in a particular data frame. As soon as an initial value is determined for both the maximum positive and negative peak frequencies (e.g., after the first occurrence of a “11” and a “00”, in any order), fine-stage automatic frequency compensation can be initiated. Subsequent adjustments to the VCO of the local oscillator will further refine the frequency offset towards the ideal of zero.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A glitchless clock switch in accordance with the principles of the present invention avoids the need to directly synchronize clock selection signals with the source clock. Instead, clock switching control signals are generated with relation to Finite-State-Machines (FSMs) for each clock signal. Thus, the cycle relationship of the different clock sources do not affect the clock switching process. The FSM for each clock has three states: ON, STOP, and IDLE. During the switching process, each clock signal enters its respective IDLE state. Detection of the ALL_IDLE state is synchronized with a directly derived signal from the newly selected clock. Any glitches in the switching process are isolated to the control of the synchronization of the ALL_IDLE state, which does not affect the output clock signal.

Abstract: A method for reducing skew in a common signal as applied to individual elements in the design phase. In accordance with the principles of the present invention, the design of the wiring is established and augmented with compensation elements and/or delay elements as necessary to equalize the skew as between all relevant components. In the disclosed embodiment, the method generally comprises three general steps: (1) grouping loads on the common signal; (2) creating a signal wiring tree and inserting delay cells; and (3) providing necessary loading compensation. The loads are grouped such that each utilized node on a central wiring experiences substantially equal loading, with compensating loads added as necessary. The nodes are established at intervals corresponding to the availability of delay elements, which are added to the branches feeding the farthest elements as necessary to equate the time delay of each node with respect to the source of the common signal.

Abstract: An asynchronous wait state generator circuit and method is included in a dual port device, e.g., in a dual port memory, to allow the use of separate address decoders and simultaneous access to memory locations from asynchronously operating, separate ports. When an address collision is detected between accesses on both ports of a dual port device, a wait state signal is generated for the relevant port having the later attempt to access the same memory or other addressable location. In the unique event wherein both accesses are initiated at precisely the same time, a meta-stable element is used to resolve the condition and to allow access to a prioritized port. The wait state signals output for the relevant port of the dual port device are preferably synchronized with the clock signal of the relevant port.

Abstract: The present invention includes a voltage control circuit having at least one voltage-controlled oscillator and at least one voltage controller connected to the voltage controlled oscillator. The voltage controller has at least one voltage input for supplying an input voltage to the voltage controller, a control signal input for supplying a control signal to the voltage controller, and a voltage output connected to the voltage controlled oscillator for supplying an output voltage thereto. The output voltage controls the delay of the voltage controller oscillator by supplying the control signal to the voltage controller.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A new memory cell design having differential and dedicated read and write ports is disclosed. The memory cell utilizes separate write and read bit lines. The read bit lines are pre-charged to a first level. A grounding transistor is provided between the circuitry containing the cell's contents and the read bit lines such that the contents of the cell are isolated from the read bit lines. The grounding transistor is activated and deactivated by the data within the cell. The activation and deactivation of the grounding transistor causes the pre-charged bit lines to be pulled-down to a second level or to remain at the first level to accurately reflect the contents of the cell. Since the circuitry containing the contents of the cell is isolated from the read bit lines, a read operation on the cell will not interfere with an in progress write operation and thus, destruction of the cell's contents is prevented. In addition, the isolation prevents bit line coupling.

Abstract: A for Fast Fourier Transform (FFT) address generator utilizes a butterfly counter to count a butterfly count for each butterfly stage of FFT in numerical sequence; and a stage counter to count a stage count for the butterfly stage of FFT in bit-shifting manner. A data address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a data address according to a first regularized logic function. A twiddle factor address logic is coupled to the butterfly counter and the stage counter to receive the butterfly count and the stage count, and to generate a twiddle factor address according to a second regularized logic function.

Abstract: A block floating point mechanism for a Fast Fourier Transform processor utilizes a pipelined butterfly processor to receive the source data to be computed, to perform the butterfly computations, and to output the resultant data. A shifter is coupled to the pipelined butterfly processor to receive the resultant data for shifting the resultant data by the largest overflow bit number occurring in the previous stage of butterfly computations. An overflow detector is coupled to the shifter to receive the shifted resultant data for detecting the largest overflow bit number occurring in this stage of butterfly computations, and for sending the detected largest overflow bit number to the shifter.