Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: The disclosure provides a wide-angle lens, an imaging module, and a camera. From an object side to an imaging plane, the wide-angle lens sequentially includes: a first lens and a second lens each having a negative refractive power, a convex object side surface, and a concave image side surface; a third lens having a positive refractive power and a convex image side surface; a fourth lens having a negative refractive power, a concave object side surface, and a convex image side surface; a stop; a fifth lens; a sixth lens; a seventh lens having a negative refractive power, a concave object side surface, and a concave image side surface; an eighth lens; and an optical filter. The fifth lens, the sixth lens, and the eighth lens each have a positive refractive power, a convex object side surface, and a convex image side surface.

Abstract: A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.

Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.

Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor and memory cells, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program/verify cycle, program a target memory cell of the memory cells in a select memory string of the memory strings, and after programming the target memory cell, verify the target memory cell using one or more verify voltages including an initial verify voltage. The peripheral circuit is also configured to compare the initial verify voltage with a threshold verify voltage so as to obtain a comparing result, and control, at least based on the comparing result, the DSG transistor in an unselect memory string of the memory strings between programming and verifying the targe memory cell.

Abstract: An optical imaging lens group, from an object side to an image side sequentially includes: a meniscus-shaped first lens having a negative refractive power and a convex surface facing the object side; a meniscus-shaped second lens having a negative refractive power and a convex surface facing the image side; an aperture stop; a third lens having a positive refractive power and two convex surfaces respectively at the object side and the image side; a fourth lens having a positive refractive power and two convex surfaces respectively at the object side and the image side; a fifth lens having a negative refractive power and two concave surfaces respectively at the object side and the image side; a sixth lens having a positive refractive power and two convex surfaces respectively at the object side and the image side; and a filter.

Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Abstract: An operation method for a 3D NAND flash including a plurality of wordline (WL) layers. The operation method includes: writing data into a WLn layer of the plurality of WL layers according to a writing sequence from a first end of the plurality of WL layers to a second end of the plurality of WL layers in a write operation, wherein the WLn layer is a selected WL layer; and applying a first pass voltage on a first WL layer of the plurality of WL layers and applying a second pass voltage on a second WL layer of the plurality of WL layers during a verify phase; wherein the operation method is operated without a pre-pulse phase during or before the verify phase.

Abstract: A programming method for a memory device is disclosed. The programming method comprises moving a plurality of first charge carriers at a shallow energy level to a channel in a substrate layer before a fine programming operation for a first word line, wherein the plurality of first charge carriers at the shallow energy level correspond to a memory cell to be programmed.

Abstract: The disclosure provides an ultra-wide-angle lens. From an object side to an imaging surface, the ultra-wide-angle lens sequentially includes a first group with a negative refractive power, a second group with a positive refractive power, a stop, a third group with a positive refractive power or negative refractive power, a fourth group with a positive refractive power and filter. The first group includes at least one negative refractive power lens, the second group sequentially includes a negative refractive power lens and a positive refractive power lens. The third group includes a positive refractive power lens and a negative refractive power lens, the positive refractive power lens of the third group and the negative refractive power lens of the third group being bonded together to form an integrated body. The fourth group includes at least one positive refractive power lens.

Abstract: The disclosure provides an optical lens system and a vehicle camera. From an object side to an imaging surface, the optical lens system sequentially includes a first lens having a negative refractive power; a second lens having a positive refractive power; a third lens having a positive refractive power; a fourth lens having a positive refractive power; a fifth lens having a negative refractive power, the fourth lens and the fifth lens constituting a cemented lens; a sixth lens having a positive refractive power; a seventh lens with a negative refractive power; a stop disposed between the first lens and the third lens. The lens of the present disclosure not only has thermal stability, but also has extremely high resolution for the objects that emit or reflect monochromatic lights of different wavelengths, so as to meet the requirements of the driverless vehicle system on the lens.

Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.

Abstract: A memory device includes a memory array including a cell, and a controller coupled to the memory array. The controller is configured to control sequentially applying programming voltage pulses to the cell. A pulse width of each of the programming voltage pulses decreases as a pulse count of the programming voltage pulses increases.

Abstract: Provided is an endoscope lens, a camera module and an endoscope. From an object side to an image side, the endoscope lens sequentially includes: a first lens having a concave object side surface and a convex image side surface; a second lens with a positive or negative refractive power; and a filter arranged between the second lens and the image side. Each of the first lens and the second lens is a glass or plastic aspheric lens. The endoscope lens further includes a stop positioned between the first lens and the object side or between the first lens and the second lens.

Abstract: An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.

Abstract: In a memory device which includes a plurality of memory cells, a top dummy storage region, a bottom dummy storage region, a plurality of word lines and a plurality of bit lines form in a substrate, a selected bit line among the plurality of bit lines, a channel region in the substrate and a source region in the substrate are pre-charged and a negative pre-pulse voltage is applied to the bottom dummy storage region during a first period. A selected memory cell among the plurality of memory cells is programmed during a second period subsequent to the first period, wherein the selected memory cell is coupled to the selected bit line and a selected word line among the plurality of word lines.

Abstract: A control method of a programming process for a three-dimensional (3D) NAND flash memory array comprises programming a bit-cell of the 3D NAND flash memory array in a programming stage; and verifying whether the bit-cell of the 3D NAND flash memory array is programmed in a verification stage after the programming stage; wherein the programming stage comprises programming the bit-cell of the 3D NAND flash memory array with a plurality of programming voltage pulses; wherein the verification stage comprises reading the bit-cell of the 3D NAND flash memory array with lower or higher voltage than normal reading voltage pulse.

Abstract: An operating method and a non-volatile memory device are provided. The non-volatile memory device includes a memory array including a plurality of memory cells. The operating method includes applying a first program voltage signal to selected word lines connected to selected memory cells during a first program period and measuring a first threshold voltage, applying a second program voltage signal to the selected word lines during a second program period and measuring a second threshold voltage, applying a test bit line voltage signal to selected bit lines and applying a third program voltage signal to the selected word lines during a third program period and measuring a third threshold voltage and determining the enhanced bit line voltage by comparing a difference between the third threshold voltage and the second threshold voltage with a difference between the second threshold voltage and the first threshold voltage.

Abstract: An operation method for a 3D NAND flash includes writing data into a WLn layer of the plurality of wordline layers of an unselect bit line of the plurality of bit lines in a write operation; and applying a first pass voltage on at least a first WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines and applying a second pass voltage on at least a second WL layer of the plurality of wordline layers of the unselect bit line of the plurality of bit lines; wherein the operation method is operated when a pre-pulse phase is removed from a verify phase.

Abstract: A programming method of an increment step pulse program (ISPP) for a three-dimension (3D) NAND flash includes programming a select wordline of an unselect bit line of the 3D NAND flash; performing a first verification process with at least a verification voltage on the select wordline; determining whether a first verification voltage of the first verification process for the select wordline is higher than a default voltage or not; and removing a pre-pulse phase of the ISPP when the first verification voltage is higher than the default voltage; wherein the first verification voltage is a following verification voltage of the first verification process.