Abstract: The disclosed technology generally relates to methods of fabricating magnetic memory devices, and more particularly to methods of forming a magnetic tunnel junction (MTJ) stack. In one aspect, a method of forming the MTJ includes providing an MTJ material stack comprising a ferromagnetic material and forming thereon a protective mask layer to cover an active area of the MTJ material stack. The method additionally includes incorporating a glass-forming element into exposed portions of the ferromagnetic material. The method additionally includes at least partially amorphizing the exposed portions of the ferromagnetic material, wherein at least partially amorphizing transforms the exposed portions of the ferromagnetic material into an electrical insulator.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

Abstract: Device and method for monitoring a plasma in a chamber of a plasma reactor is are disclosed. In one aspect, the method includes measuring plasma parameter data at a surface of a single planar Langmuir probe in contact with the plasma. A biasing capacitor is connected between the single planar Langmuir probe and a DC-bias source. Subsequently a discharge current of the biasing capacitor as a result of the DC-bias is measured, and a probe potential at the single probe during the discharge is measured. The measurements can be used to detect presence and/or thickness of a dielectric film on the probe surface.

Abstract: A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.

Abstract: A plasma composition and its use in a method for the dry etching of a stack of at least one material chemically too reactive towards the use of a Cl-based plasma are provided. Small amounts of nitrogen (5% up to 10%) can be added to a BCl3 comprising plasma and used in an anisotropical dry etching method whereby a passivation film is deposited onto the vertical sidewalls of stack etched for protecting the vertical sidewalls from lateral attack such that straight profiles can be obtained.

Abstract: A method for patterning a dual damascene structure in a semiconductor substrate is disclosed. The patterning is a metal hardmask based pattering eliminating at least resist poisoning and further avoiding or at least minimizing low-k damage. The method can be used as a full-via-first patterning method or a partial-via-first patterning method.

Abstract: The present invention concerns a method for stripping the photoresist layer and the crust from a semiconductor. The crust has been formed with as a result of an ion implantation step, wherein the method comprises an ion assisted plasma step using a mixture of water vapour, helium and a F-containing compound in which radicals are generated, and the step of contacting said photoresist layer and crust with said radicals to remove said photoresist layer and crust from said semiconductor surface. Said plasma step is preferably an ion assisted plasma step.