Abstract: An input circuit for a field effect transistor (FET) storage is described which consists of a bootstrap inverter which by a dynamically operating charge-up circuit is supplemented for charging up the bootstrap node to the full operating voltage, and which can be directly controlled with TTL levels without a level converter consisting of bipolar transistors being inserted. For that purpose, the input electrode of the bootstrap capacitor of the dynamically operating charge-up circuit is connected to the output of an inverter following the input circuit. Furthermore a discharge branch is provided for the node of the dynamically operating charge-up circuit. With its other end, together with the gate of the charge-up field effect transistor of the dynamic charge-up circuit, the discharge branch is connected to the output of another inverter following the first one.

Abstract: An apparatus for transferring ink to the printing plate of a metering head of a metering machine has an ink storage roller mounted on a roller support with which it is interchangeably inserted through a lateral opening in the metering machine casing. On one end of the roller support, a handle is provided which is located laterally on the casing, thereby preventing contact with the ink storage roller during replacement. The insertion of a new ink storage roller is facilitated by a fixed bearing bolt on which is mounted the hollow shaft of the roller support. A protective sleeve connected to the back of the casing wall prevents unauthorized access to the metering head of the metering machine through the casing opening.

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

Abstract: A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.

Abstract: To the known sense latch already existing in a bit line pair in an FET memory, and to the two bit switches in each bit line another latch is arranged in series which furthermore is coupled to the common data input and output via a write driver on the one side and a read driver on the other. Both latches are of an identical structure and controlled by the same pulses in the read as well as in the write phase. The data path via the write driver and the read driver up to, or from, the additional latch is respectively designed as unidirectional double rail line, and selectively connectable via the bit switches with the bidirectional double rail line to the respective bit line pair.

Abstract: Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.

Abstract: A device for transmitting information in the form of an electrical signal to at least one mechanism for giving a readout of the information, comprises a readout mechanism which has at least one symbol wheel which carries symbols on its circumference. A plurality of angularly spaced and radially extending actuating members are affixed to a drive shaft which rotates to move the actuating members in a first plane. The actuating members are divertible into a second plane parallel to the first plane by a switch arranged in the plane of movement of the actuators so as to selectively divert the actuating members into a second plane. The actuating members have individual symbols corresponding to the number of readout symbols and guide walls are provided for supporting the actuators and the switch, as well as a gear drive for a symbol wheel in the respective first and second planes. A relay is employed for sensing the symbol position of the symbol wheel and it is connected to the switch to energize the switch.

Abstract: A semiconductor storage circuit for use in monolithic memories. The circuit is comprised of a storage cell coupled to input-output bit lines through active devices having symmetrical conduction properties. The storage cell can be comprised of a pair of cross coupled bipolar transistors having resistors as collector load devices. Schottky field effect transistors (MESFET's) are active devices having symmetrical conduction properties.The entire circuit of the invention is readily created in integrated form in semiconductor wafers using existing processes.