Abstract: A phase locked loop system for generating a line-locked clock signal for a television signal processing system includes an analog phase-locked loop nested within a digital phase locked loop. The analog phase-locked loop is synchronized to a reference signal which is derived from the most significant bit of a digital oscillator signal generated by a clocked digital oscillator. To reduce instability in this reference signal, the ratio of the frequency of the clock signal to the frequency of the digital oscillatory signal is chosen to be a noninteger value greater than two. In one embodiment of the invention the stability of the reference signal is further enhanced by adaptively delaying transitions in the reference signal by amounts of time that are inversely proportional to the value of the less significant bits of the samples corresponding to the transitions.

Abstract: A transition enhancing circuit includes a tapped delay line which provides successively delayed replicas of the signal to be processed. A multiplexer, responsive to a signal transition, sequentially couples delayed signal from the center tap and taps more distant from the input of the delay line to an output terminal to effectively hold the initial value of the transition for approximately half the transition period. The taps at the input end of the delay line up to and including the center tap are then sequentially coupled to the output terminal to effectively advance, in time, the end value of the signal transition. The signal transition is thereby reduced to a time equivalent to the switching interval between taps.

Abstract: An interline comb filter for separating luminance signal from composite video includes a subcarrier trap which is selectively engaged in the comb filtered luminance signal path to remove "hanging dots". Control for the subcarrier trap is provided from vertical detail signals.

Abstract: A digital video signal processing system is described wherein analog video signal is sampled by a sampling clock phase locked to burst and the digital video samples are processed with a clock phase locked to horizontal sync. The respective sampling phases of the sampling clock are encoded and concatenated with the digital video samples for purposes of synchronously demodulating the color difference signals of composite video. Burst clock to line locked clock sample conversion is accomplished in a FIFO memory.

Abstract: A processor, for providing a double line-rate video output signal comprising alternating received lines and interpolated lines, comprises three memories. As each line of incoming video signal is stored in one of the three memories, at a given clock rate the remaining two memories are read at double the write clock rate. A single averaging circuit, having inputs selectively coupled to the memories, interleaves non-interpolated time compressed lines of video obtained from one of the two memories being read with time-compressed lines of video obtained by interpolation from both of the two memories being read to provide a processed video output signal. The "write-one read-two" memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up.