Abstract: An electronic power unit has a substrate with a perpendicular direction and a flat insulating molded body has a metal layer on a first main face and conductor tracks on a second main face. The substrate is in a non-positive locking or materially-bonded manner on a base plate of the electronic power unit. A first fastening device is on the base plate in a non-positive locking manner on a cooling device or a housing section has a second fastening device provided to arrange the substrate in a non-positive locking manner on a cooling device.

Abstract: An electronic power unit has a substrate with a perpendicular direction and a flat insulating molded body has a metal layer on a first main face and conductor tracks on a second main face. The substrate is in a non-positive locking or materially-bonded manner on a base plate of the electronic power unit. A first fastening device is on the base plate in a non-positive locking manner on a cooling device or a housing section has a second fastening device provided to arrange the substrate in a non-positive locking manner on a cooling device.

Abstract: An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.

Abstract: An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank region and being alternately connected to an m-bit data bus. The memory banks are classified into two groups, each group including a memory bank of each memory bank region. The memory module further includes a selection device connected to the memory banks and being responsive to selection bits. The selection device selects one of the two groups of memory banks and a group of i memory cells within the memory banks of the selected group of memory banks to access the selected i memory cells per one stroke via the associated m-bit data buses of the memory groups including the selected memory banks, m being equal to an integer multiple of i.

Abstract: In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.

Abstract: In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.

Abstract: The invention relates to two methods for reading and two methods for storing data, and also to an apparatus for compressing data and decompressing data which are provided for storage by a computer system 51 on a bulk memory 60 of the random access type, which computer system provides the data for storage on a bulk memory on the basis of the rules of a file system, where the data are organized in data blocks, where the data blocks contain organization information for managing the data blocks and contain the user information which is to be stored, where cohesive user information areas can be distributed over a plurality of data blocks which are then concatenated to one another using their organization information.

Abstract: Method for storing data, method for reading data, apparatus for storing data and apparatus for reading data