Abstract: A parasitic field effect transistor or a parasitic diode is formed in an integrated circuit. The parasitic element is formed by two doped regions of the same or opposite conductivity type and an insulating region therebetween. The doped regions are each connected to a respective terminal pad of the integrated circuit. To increase the ESD strength, the length of the insulating region in the lateral direction is greater than or equal to a length of the longest discharge path of the ESD protection structures connected to the terminal pads.

Abstract: An integrated semiconductor circuit includes a semiconductor substrate. A number of first potential buses carry a first supply potential of the semiconductor circuit during operation. A number of second potential buses carry a second supply potential of the semiconductor circuit during operation. A number of circuit portions formed on the substrate are each connected between one of the first and one of the second potential buses for being supplied with electrical voltage. Connection points are formed on the substrate and are each assigned to one of the circuit portions for receiving an input or output signal for the circuit portion during operation of the circuit portion. Protective circuits are formed on the substrate and are each assigned to one of the circuit portions for preventing overvoltage. The protective circuits each have an input side connected to one of the connection points and an output side connected to the circuit portion.

Abstract: A fuse bank includes a fuse link being disposed above and insulated from a substrate. A first doped region in the substrate is a guard ring surrounding the fuse link. A second doped region has the same conduction type as the first doped region and is adjacent the first doped region. An insulation separates the second doped region from the first doped region. A high-impedance semiconductor component connects the first doped region to a first supply potential. The second doped region is connected to a second supply potential.

Abstract: A semiconductor component includes a semiconductor body having a terminal pad, a semiconductor function element, and an electrically conductive connecting line connecting the terminal pad to the semiconductor function element. A protective element for protecting against electrostatic discharge is connected between the terminal pad and the semiconductor function element. A first supply line for a first supply potential is connected to the semiconductor function element. A second supply line for the first supply potential is connected to the protective element and is electrically conductively connected to the first supply line. A clamp element is connected to the connecting line and to the first supply line, for limiting a voltage applied to the clamp element to a clamp value.

Abstract: An integrated semiconductor circuit includes a semiconductor substrate. At least one first and at least one second potential rail respectively carry first and second supply potentials of the semiconductor circuit during operation. At least one input signal line has at least one input signal terminal and at least one output signal line has at least one output signal terminal and at least one additional line connected to the output signal terminal. At least one first circuit portion receives and processes input signals and at least one second circuit portion develops at least one output signal of the semiconductor circuit during operation of the semiconductor circuit. A configuration for protection against overvoltages has a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and has a second protection circuit for each output signal terminal being connected to the additional line.

Abstract: Integrated circuit having anti latch-up circuit in complementary MOS circuit technology. Due to the incorporation of non-linear elements between the ground (V.sub.ss) and the p-conductive semiconductor substrate (P.sub.sub) and between the supply voltage (V.sub.DD) and the n-conductive semiconductor zone (N.sub.w), the risk of the occurrence of the latch-up effect triggered by the build-up of base charges at the parasitic vertical and lateral bipolar transistors is diminished. The space requirement for the non-linear elements to be additionally incorporated is low and the circuit properties of the MOS transistors are not influenced as a result thereof. The realization of the non-linear elements can ensue with Schottky contacts or with additional MOS transistors that are wired as diode elements. A realization in the form of buried diodes of polycrystalline silicon (PSi) is also possible, realized, for example, as barrier layer diodes.

Abstract: The risk of a latch-up is diminished by the incorporation of an additional bypass transistor between the output (OUT) and the supply voltage (V.sub.DD) of an integrated circuit, for example a CMOS output stage. In case positive over-voltages that are greater than the sum of the supply voltage (V.sub.DD) and the conducting-state voltage of the bypass transistor occur at the output (OUT), the bypass transistor becomes conductive and represents a low-impedance connection between the output (OUT) and the supply voltage (V.sub.DD). In this case, the bypass transistor (BT) suctions additional charge carriers off and thereby increases the trigger current needed for the appearance of latch-up. The incorporation of an additional bypases transistor is possible both given well-shaped semiconductor zones that lie at a fixed potential as well as given well-shaped semiconductor zones that are wired to a variable potential. FIG.

Abstract: An integrated circuit has a storage cell and complementary MOS-circuit technology. A substrate bias voltage generator connects a semiconductor substrate having a well region inserted therein to a substrate bias voltage. In order to avoid latch-up effects, an electronic protection circuit connects a current path, for charging a capacitor of the storage cell, only after a delay time .DELTA.T following a switch-on of the integrated circuit.

Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit.

Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum.