Abstract: A method of forming sublithography gate lengths involves the steps of patterning the layer of resist above the gate stack (including a gate layer, hardmask layer and etch-control layer) to a desired gate length and etching the etch-control layer and the hardmask layer; the portion of the circuit that has the correct gate length is covered with a blocking mask and the hardmask in the remainder is wet-etched to reduce its dimension, after which the gate stack is etched using both gate lengths of hardmask to produce different gate lengths in different areas.

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/&mgr;m or below) and a channel length (sub-lithographic, e.g., 0.1 &mgr;m or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.

Abstract: Techniques to fabricate sub−0.05 &mgr;m MOSFET devices with Super-Halo doping profile which provide excellent short-channel characteristics are provided. The techniques utilize a damascene-gate process to obtain MOSFET structures with oxide thickness above the source/drain region independent of the gate-oxide thickness and a disposable-spacer technique for the formation of the Super-Halo doping profile.

Abstract: A dielectric wiring structure and method of manufacture therefor. Successively formed wiring layers synergistically combine with subsequently formed sidewall supports spanning two or more layers to form a self supporting air dielectric interconnection matrix. Wires are supported by vertical nitride sidewalls which are, in turn, held in place and supported by the wires. After forming the complete wiring-sidewall structure, SiO2 between and under the wires is removed using gaseous HF at a partial pressure between 5 and 30 Torr. The metal wires may be clad with nitride for short and oxidation protection. Because sidewalls are formed after wiring, with the wiring at each level providing support definition, complex support alignment is unnecessary.

Abstract: A dielectric wiring structure and method of manufacture therefor. Successively formed wiring layers synergistically combine with subsequently formed sidewall supports spanning two or more layers to form a self supporting air dielectric interconnection matrix. Wires are supported by vertical nitride sidewalls which are, in turn, held in place and supported by the wires. After forming the complete wiring-sidewall structure, SiO.sub.2 between and under the wires is removed using gaseous HF at a partial pressure between 5 and 30 Torr. The metal wires may be clad with nitride for short and oxidation protection. Because sidewalls are formed after wiring, with the wiring at each level providing support definition, complex support alignment is unnecessary.

Abstract: A film layer not susceptible to aerosol cleaning is removed from a surface by converting the film layer into a film susceptible to aerosol cleaning, and aerosol jet cleaning the converted film and any contaminants. The aerosol jet can be moved in relation to the surface to provide thorough cleaning.