Patents by Inventor Wesley COTTELEER

Wesley COTTELEER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11838667
    Abstract: A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a plurality of pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: December 5, 2023
    Assignee: AMS SENSORS BELGIUM BVBA
    Inventor: Wesley Cotteleer
  • Patent number: 11770640
    Abstract: An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 26, 2023
    Assignee: AMS SENSORS BELGIUM BVBA
    Inventor: Wesley Cotteleer
  • Publication number: 20220166947
    Abstract: A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a pluralityof pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.
    Type: Application
    Filed: February 5, 2020
    Publication date: May 26, 2022
    Inventor: Wesley COTTELEER
  • Publication number: 20220150438
    Abstract: An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.
    Type: Application
    Filed: February 5, 2020
    Publication date: May 12, 2022
    Inventor: Wesley COTTELEER