Patents by Inventor Wesley Queen

Wesley Queen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11650765
    Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: May 16, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Raj Ramanujan, Kuljit Singh Bains, Liyong Wang, Wesley Queen
  • Publication number: 20220050600
    Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Inventors: Raj RAMANUJAN, Kuljit Singh Bains, Liyong Wang, Wesley Queen
  • Patent number: 11194524
    Abstract: A processing system for performing persistent write operations comprises a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command. The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host. Persistent Write completion indications may be provided to the host in a different order from an order in which corresponding commands were received. Statuses of Persistent Write commands may be maintained in a completed bitmap or a pending bitmap. A FLUSH command may be provided to indicate that all prior writes buffered in volatile media are to be pushed to non-volatile or persistent memory.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 7, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Raj Ramanujan, Kuljit Singh Bains, Liyong Wang, Wesley Queen
  • Patent number: 11016669
    Abstract: In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 25, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kuljit Singh Bains, Raj Ramanujan, Liyong Wang, Wesley Queen
  • Patent number: 10996888
    Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 4, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kuljit Singh Bains, Raj Ramanujan, Wesley Queen, Liyong Wang
  • Patent number: 10884639
    Abstract: Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: January 5, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Liyong Wang, Kuljit Singh Bains, Wesley Queen
  • Patent number: 10503435
    Abstract: Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems is disclosed. In one aspect, a processor-based system includes a DRAM circuit (e.g., disposed on a common x4/x8 die) providing 4-bit-wide data access (“x4”) and a 128-bit internal data prefetch. When operated in a x4 mode, the DRAM circuit is configured to provide an extended DRAM burst length of 32 bits (“BL32”). The DRAM circuit receives a memory read request from a memory controller communicatively coupled to the DRAM circuit, prefetches 128 bits of data, and returns all of the 128 bits of fetched data to the memory controller in response to the memory read request. In some aspects, the DRAM circuit may also receive a memory write command including 128 bits of write data from the memory controller, and write the 128 bits of write data to memory without performing a read/modify/write (RMW) operation.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 10, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Kuljit Singh Bains, Wesley Queen, Liyong Wang
  • Publication number: 20190339865
    Abstract: In non-energy-backed memory with persistent storage, a complex protocol is required to handle persistent writes. To address this issue, it is proposed to provide a simple protocol to handle persistent writes in energy-backed memory with persistent storage.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Kuljit Singh BAINS, Raj RAMANUJAN, Liyong WANG, Wesley QUEEN
  • Publication number: 20190129656
    Abstract: Systems and methods for synchronizing write credits between a host device and a media controller of a memory system comprising a non-volatile memory (NVM), wherein the host device is configured to maintain a write credit (WC) counter implemented in a memory controller of the host device. The WC counter tracks and limits the number of outstanding write commands which may be issued to the NVM. The host device may query the memory system to obtain status of the available write buffer space in the media controller, and adjust the WC counter based on any detected errors in the write buffer space reported in metadata of read packets sent from the memory system.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 2, 2019
    Inventors: Kuljit Singh BAINS, Raj RAMANUJAN, Wesley QUEEN, Liyong WANG
  • Publication number: 20190087096
    Abstract: Systems and methods for persistent operations include a host and a memory system. The memory system, upon receiving a Persistent Write command and associated write data from the host, performs a Persistent Write of the write data to a non-volatile memory in the memory system based on the Persistent Write command The memory system may also a receive a write identification (WID) associated with the Persistent Write command from the host and provide, upon successful completion of the Persistent Write, a Persistent Write completion indication along with the associated WID to the host.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Inventors: Raj RAMANUJAN, Kuljit Singh BAINS, Liyong WANG, Wesley QUEEN
  • Publication number: 20180246665
    Abstract: Aspects of the disclosure are directed to providing a single data rate (SDR) mode or a double data rate (DDR) mode to a Registering Clock Drive (RCD) for a memory. Accordingly, the apparatus and method may include determining data rate mode selection criteria; selecting a data rate mode based on the data rate mode selection criteria; configuring a host interface for the data rate mode; and configuring an RCD input interface for the data rate mode. In one aspect, the apparatus and method further include activating a clock signal on the host interface and on the RCD input interface; transferring data from the host interface to the RCD input interface using the clock signal; and transferring the data from an RCD output interface using the clock signal in either 1N mode or 2N mode. And, the data rate mode is one of the SDR mode or the DDR mode.
    Type: Application
    Filed: February 21, 2018
    Publication date: August 30, 2018
    Inventors: Liyong Wang, Kuljit Singh Bains, Wesley Queen
  • Publication number: 20180157441
    Abstract: Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems is disclosed. In one aspect, a processor-based system includes a DRAM circuit (e.g., disposed on a common x4/x8 die) providing 4-bit-wide data access (“x4”) and a 128-bit internal data prefetch. When operated in a x4 mode, the DRAM circuit is configured to provide an extended DRAM burst length of 32 bits (“BL32”). The DRAM circuit receives a memory read request from a memory controller communicatively coupled to the DRAM circuit, prefetches 128 bits of data, and returns all of the 128 bits of fetched data to the memory controller in response to the memory read request. In some aspects, the DRAM circuit may also receive a memory write command including 128 bits of write data from the memory controller, and write the 128 bits of write data to memory without performing a read/modify/write (RMW) operation.
    Type: Application
    Filed: November 29, 2017
    Publication date: June 7, 2018
    Inventors: Kuljit Singh Bains, Wesley Queen, Liyong Wang