Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

Abstract: Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a mainboard or other circuit board may be referred to as a direct-chip attach (DCA) die. A package is disposed over at least a portion of the DCA die and coupled with the mainboard. The package includes one or more other IC die disposed on a substrate. Other embodiments are described and claimed.

Abstract: A microelectronic package and a method of forming the package. The package includes a first level package mounted to a carrier. The first level package includes a package substrate having a die side and a carrier side; and a microelectronic die mounted on the package substrate at the die side thereof. The carrier has a substrate side, and the first level package is mounted on the carrier at the substrate side thereof. A rigid body is attached to the carrier side of the substrate at an attachment location of the substrate and to the substrate side of the carrier at an attachment location of the carrier, the attachment location of the carrier being electrically unconnected, the rigid body being configured and disposed to provide structural support between the substrate and the carrier.

Abstract: Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias in the printed circuit board may be aligned into a planar line with a set corridor spacing between adjacent of groups of vias also aligned into a planar line with the same axis to allow a routing space for lines in multiple layers of the printed circuit board to occur in the routing space established by the set corridor spacing.

Abstract: A method includes providing a light pipe having a metallized end surface, and soldering the metallized end surface of the light pipe to a surface of a substrate. Other embodiments are described and claimed.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: Apparatus and methods of fabricating antennae embedded within a ceramic material, such as a low temperature co-fired ceramic. Such ceramic material has a low coefficient of thermal expansion which reduces expansion and contraction stresses that can cause the signal transmission frequency to change and thereby affecting proper signal transmission.

Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.

Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: A system to package high performance microelectronic devices, such as processors, responds to component transients. In one embodiment, the system includes a decoupling capacitor that is disposed between a Vcc electrical bump and a Vss electrical bump. The decoupling capacitor has Vcc and Vss terminals. The Vcc and Vss terminals share electrical pads with the Vcc electrical bump and the Vss electrical bump. A simple current loop is created that improves the power delivery for the system.

Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.

Abstract: A socket may comprise an array of first contacts and a set of second contacts having a greater conductive cross-sectional area than the first contacts. The set of second contacts may also have a greater conductive area efficiency than the array of first contacts, with conductive area efficiency defined as a total conductive cross-sectional area divided by a total occupied area. The array of first contacts may electrically couple signal pads of a land grid array (LGA) component with a plurality of signal lines in a printed circuit board (PCB). The set of second contacts may electrically couple power delivery land pads of the LGA component with power and ground planes of the PCB.

Abstract: A method and apparatus to thermally control multiple electronic components, such as field-effect transistors for voltage regulation in processors and chipsets in computers, allow more effective convective cooling by grouping the electronic components in an at least essentially closed loop configuration about a passageway which is open at both ends to permit air flow therethrough. The electronic components form respective side walls of the passageway or are in heat conducting relation with the side walls of a heat sink which forms the passageway. Mounting the electronic components to stand upright off the motherboard allows air to enter below the components and rise up through the passageway producing an increase in air speed and better convective cooling.