Abstract: A power FET and a replica FET on a semiconductor chip coupled to a logic control circuit on a second semiconductor chip within a single housing. A power FET and a scaled down replica of the power FET are disposed on a semiconductor chip. The power FET is used as a switch to couple a DC power source to a load. A fraction of the power FET drain current passes through the replica FET and an external resistance. When the voltage across the external resistance exceeds a maximum value based upon the maximum allowable power FET drain current, the logic control circuit enters into a pulsed gate (PG) mode of operation. The first step in the PG mode is to switch both FETs into a non-conducting state for a predefined period of time. After this time period, a ramp voltage applied between gate and source of both FETs will switch them back into a current conducting state while holding the power FET drain current below its upper limit in the presence of a high capacitance load.

Abstract: A generally rectangular heat sink is mounted in a conduit box by tabs which are deformed to fit within channels along opposite edges of the heat sink. An access hole in the side of the conduit box and aligned with the channel permits a pin to be inserted therethrough to push the tabs out of the channel and release the heat sink and PC board from the conduit box.

Abstract: A D.C. brushless motor with a permanent magnet rotor employs Hall switches to effect commutation. The rotor magnets are of a greater axial length than the stator stack and the Hall switches are mounted on a printed circuit panel within the motor frame so as to be actuated by the fringe flux from the portion of a rotor magnet extending beyond the stator stack. The pole faces of the stator stack are stepped to assure proper starting and direction of rotation. A voltage regulating circuit forming part of the commutating arrangement on the printed circuit panel enables the same circuit to be used for a range of stator energizing voltages.