Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.

Abstract: A level detector, a voltage generator, and a semiconductor device are provided. The voltage generator includes a level detector that senses the level of an output voltage to output a sensing signal and a voltage generating unit that generates the output voltage in response to the sensing signal. The level detector may include a first reference voltage generator configured to divide a first voltage and to output a first reference voltage, a second reference voltage generator configured to divide a second voltage in response to the output voltage and to output a second reference voltage that varies as a function of temperature, and a differential amplifier configured to receive the first and second reference voltages and to output a sensing signal in response to a sensing voltage generated by amplifying a difference between the first and second reference voltages.