Abstract: LED devices or circuits include a number of serially connected LED segments, which may additionally include parallel branches, which are switched on or off depending on an input voltage to the LED segments. As the input voltage varies, none, different portions, or all of the LEDs are lit. The input voltage to the LED segments may be an output voltage from a bridge rectifier in response to an alternate current (AC) power. The LED devices or circuits include no inductors, transformers and electrolytic capacitors.

Abstract: The present disclosure provides an ultra high voltage (UHV) light emitting diode (LED) device. According to one embodiment, the device includes a substrate, a plurality of LED junctions disposed above the substrate and coupled to one another, and a control component including a plurality of switches embedded within the substrate and coupled to the plurality of LED junctions to control routing of current across the plurality of LED junctions.

Abstract: A method for providing control information between a host and a home phone line network via an Ethernet controller includes: determining if the control information is to be transmitted to the home phone line network or is received from the home phone line network; generating a first home phone line network data frame from a frame control frame (FCF) and a corresponding first Ethernet data frame received from the Ethernet controller, if the control information is to be transmitted to the home phone line network; and generating a second Ethernet data frame and a corresponding frame status frame (FSF) from a second home phone line network data frame received from the home phone line network, if the control information is received from the hoMe phone line network. Control information is thus provided between the host and the HPNA network via an Ethernet controller without requiring additional hardware or special interfaces.

Abstract: A method for driving an ink jet head (10) having a piezoelectric actuator (103) includes the steps of: (a) transmitting a negative electrical pulse (31) to drive the piezoelectric actuator to transform in a manner such that ink is filled into an ink chamber (102) of the ink jet head; and (b) transmitting a positive electrical pulse (32) to drive the piezoelectric actuator to transform in a manner such that the ink is ejected out of the ink chamber.

Abstract: A digital communications link, protocol and related circuits are provided which use an embedded control channel for transferring control information between different sections of an xDSL system, including within a personal computer. The control channel is included as part of a data frame structure that is suited for a multi-channel communication system, including in an xDSL communications environment.

Abstract: A digital communications link, protocol and related circuits are provided which achieve a scaleable performance rate through a combination of clock scaling and/or variable frame sizing. The system is used within a personal computer, thus allowing the latter to be interoperable with any number of different communications protocols, including xDSL based transmission standards, and to set up communications links of varying capacity and performance.

Abstract: A broadband digital communications link, protocol and related I/O circuits are provided which use an embedded control channel and a frame structure for transferring control information between different sections of a broadband system, including within a personal computer. A dedicated bus within the personal computer is used to support a variety of devices using the broadband link, and clocking is performed with a combination of bit clocks and frame clocks that are adjustable to accommodate needs of disparate types of data, including data for an xDSL communications path, xDSL samples from different analog codecs for xDSL modems, and ATM cells for an ATM interfaces. The I/O circuits include multiple bus interfaces to make them more flexibly integrated into a variety of application environments.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A digital communications link and protocol is disclosed in connection with a digital controller section and an analog CODEC section of an xDSL modem mounted on a computer motherboard. The xDSL modem is configured on the motherboard with the digital and analog sections separated so as to improve noise performance in the analog front end sections. The digital communications link is characterized by an improved architecture which includes optimally selected data signal lines, an embedded control channel, a flexible data clocking mechanism, capability for providing multiple data channels, and a preselected operational and/or control word format. These features allow a computer motherboard fitted with the digital communications link to be easily adaptable and usable with a number of different combinations of digital and analog circuits associated with xDSL modems.

Abstract: A technique for configuring multiple datapath components into a one-dimensional datapath sequence to form a datapath module that provides a specified function entails counting the number of instances in which a datapath line non-redundantly passes a datapath component in each of a plurality of different one-dimensional configurations of the datapath components for which ports of the datapath components and, as necessary, the datapath module are interconnected through datapath lines to provide the specified function. The datapath components are then placed in a particular one of the one-dimensional configurations for which the number of instances counted during the counting operation is a minimum, subject to any timing constraint. Before performing the counting and placing operations, a special procedure is preferably employed to reduce the number of configurations considered during the counting operation.

Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Abstract: A cascaded charge pump includes multiple stages each providing a (nominal) 3 volt increment. Thus a charge pump having an 18 volt range is provided using a CMOS process which normally then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Abstract: An integrated optical waveguide is constructed from a lithium niobate (LiNbO.sub.3) crystal substrate. In preferred embodiments, a diffused layer is formed proximate to one surface of the substrate by sputtering a thin layer of a zinc-related oxide (e.g., ZnO, ZnLiNbO.sub.4, or the like) onto the surface and then annealing the substrate. The resulting concentration of zinc in the diffused layer forms a waveguide having desirable optical propagation characteristics. The substrate is preferably congruent lithium niobate. In particularly preferred embodiments, the substrate is magnesium oxide (MgO) doped lithium niobate.