Patents by Inventor Wiebe Barteld De Boer

Wiebe Barteld De Boer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Suppression of n-type autodoping in low-temperature Si and SiGe epitaxy
    Patent number: 6838359
    Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous cycle.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: January 4, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Wiebe Barteld De Boer
  • Phosphorus dopant control in low-temperature Si and SiGe epitaxy
    Patent number: 6579752
    Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: June 17, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Wiebe Barteld De Boer
  • Phosphorus dopant control in low-temperature Si and SiGe epitaxy
    Publication number: 20030003646
    Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.
    Type: Application
    Filed: March 26, 2002
    Publication date: January 2, 2003
    Inventor: Wiebe Barteld De Boer
  • Suppression of n-type autodoping in low-temperature Si and SiGe epitaxy
    Publication number: 20020168791
    Abstract: A method of manufacturing a semiconductor device, which method comprises the step of epitaxially growing a stack comprising an n-type doped layer of a semiconductor material followed by at least one further layer of a semiconductor material, the stack being grown in one continuous growth cycle.
    Type: Application
    Filed: April 1, 2002
    Publication date: November 14, 2002
    Inventor: Wiebe Barteld De Boer