Abstract: An avionics system for a plane includes a plurality of nodes disposed throughout the plane, each node performing a function. The system includes an optical network in communication with the nodes and through which the nodes communicate. The system includes at least one of the nodes having a hardwired interpreter that interprets the information transmitted from another one of the nodes via the optical network. A method for operating a plane includes the steps of communicating information through an optical network between a plurality of nodes disposed throughout the plane, each node performing a function. There is the step of interpreting with at least one of the nodes having a hardwired interpreter the information transmitted from another one of the nodes via the optical network. A phostonic stack.

Abstract: An apparatus for transmitting wide spectrum white light having a plurality of plastic optical fibers. The apparatus includes a sheath housing the plurality of fibers. An apparatus for providing energy in an airplane. The apparatus includes a light source which produces wide spectrum white light. The apparatus includes a cable through which the eye-safe and fire-safe light from the light source is transmitted. The apparatus includes an avionics box to which the cable is connected that is powered by the light transmitted by the cable. An apparatus for providing energy in an airplane. The apparatus includes means for producing energy that is eye-safe and fire safe. The apparatus includes an avionics box to which the producing means is connected that is powered by the energy form the producing means. A method for providing energy in an airplane. The method includes the steps of producing wide spectrum white light from a light source.

Abstract: An avionics system for a plane includes a plurality of nodes disposed throughout the plane, each node performing a function. The system includes an optical network in communication with the nodes and through which the nodes communicate. The system includes at least one of the nodes having a hardwired interpreter that interprets the information transmitted from another one of the nodes via the optical network. A method for operating a plane includes the steps of communicating information through an optical network between a plurality of nodes disposed throughout the plane, each node performing a function. There is the step of interpreting with at least one of the nodes having a hardwired interpreter the information transmitted from another one of the nodes via the optical network. A phostonic stack.

Abstract: A data link includes an ASIC. The data link includes a heat insulation layer in contact with the ASIC. The data link includes an optical transducer layer having a plurality of transducers, with each transducer of the plurality of transducers in communication with the ASIC. Each transducer converting optical signals to electrical signals or electrical signals to optical signals. The data link includes an optical waveguide layer having a plurality of waveguides for carrying optical signals. Each waveguide of the plurality of waveguides in optical communication with a transducer, the optical waveguide layer adjacent with the insulation layer. An apparatus for data. A method for transferring data.

Abstract: A data link includes an ASIC. The data link includes a heat insulation layer in contact with the ASIC. The data link includes an optical transducer layer having a plurality of transducers, with each transducer of the plurality of transducers in communication with the ASIC. Each transducer converting optical signals to electrical signals or electrical signals to optical signals. The data link includes an optical waveguide layer having a plurality of waveguides for carrying optical signals. Each waveguide of the plurality of waveguides in optical communication with a transducer, the optical waveguide layer adjacent with the insulation layer. An apparatus for data. A method for transferring data.

Abstract: An apparatus for transmitting wide spectrum white light having a plurality of plastic optical fibers. The apparatus includes a sheath housing the plurality of fibers. An apparatus for providing energy in an airplane. The apparatus includes a light source which produces wide spectrum white light. The apparatus includes a cable through which the eye-safe and fire-safe light from the light source is transmitted. The apparatus includes an avionics box to which the cable is connected that is powered by the light transmitted by the cable. An apparatus for providing energy in an airplane. The apparatus includes means for producing energy that is eye-safe and fire safe. The apparatus includes an avionics box to which the producing means is connected that is powered by the energy form the producing means. A method for providing energy in an airplane. The method includes the steps of producing wide spectrum white light from a light source.

Abstract: An avionics system for a plane includes a plurality of nodes disposed throughout the plane, each node performing a function. The system includes an optical network in communication with the nodes and through which the nodes communicate. The system includes at least one of the nodes having a hardwired interpreter that interprets the information transmitted from another one of the nodes via the optical network. A method for operating a plane includes the steps of communicating information through an optical network between a plurality of nodes disposed throughout the plane, each node performing a function. There is the step of interpreting with at least one of the nodes having a hardwired interpreter the information transmitted from another one of the nodes via the optical network. A phostonic stack.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is coupled to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is called to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: A synchronous dynamic random access memory (SDRAM) (500) is disclosed. The SDRAM (500) operates in synchronism with differential clock signals (CLK and /CLK). A timing and control circuit (510) compares the complementary differential clock signals (CLK and /CLK) to generate an internal clock signal (CLKI). By comparing the differential clock signals (CLK and /CLK) to generate the internal clock signal (CLKI), the preferred embodiment can compensate for degradations in the differential clock signals (CLK and /CLK). In addition, by utilizing the internal timing signal (CLKI) the preferred embodiment does not have to employ more complex circuits that must operate in synchronism with the edges of both differential clock signals (CLK and /CLK).

Abstract: A packet-based data storage system (400) includes a controller (402) and a number of packet-based data storage modules (404-0 to 404-n). The data storage modules (404-0 to 404-n) receive command/address information and a command clock on module command links (412-0 to 412-n) and provide access to storage locations by way of module data links (416-0 to 416-n). The controller (402) issues command/address information and a command clock signal on a controller command link (406). Data is passed to and from the controller (402) by a controller data link (408). Load protection is provided to the controller (402) and the storage modules (404-0 to 404-n) by command re-drive circuits (410-0 to 410-n), coupled between the controller command link (406) and the module command links (412-0 to 412-n), and data re-drive circuits (414-0 to 414-n) coupled between the controller data link (408) and the module data links (416-0 to 416-n).

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is called to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: An active integrated circuit socket includes plural pin sockets receiving corresponding pins of an integrated circuit and plural socket pins making electrical contact with a printed circuit board. At least one active electronic component requiring electrical power for operation connects a pin sockets to a corresponding socket pin. The active electronic component may be a single ended input to differential output driver, a differential input to single ended output driver, a single ended to differential input/output transceiver or a voltage level shifter. These active components may include passive termination resistors. The single ended to differential transceiver may further include an enable input determining the direction of data transmission. This invention may be employed as an electronic system upgrade product including at least two active integrated circuit sockets connected via a flexible sheet including a plurality of electrical conductors connecting differential signal lines.

Abstract: According to one aspect of the present invention, a selectable integrated circuit assembly (10) is disclosed. The assembly includes a first plurality of terminals (20) for communicating information to and from an integrated circuit device and a second plurality of terminals (22) for receiving an assembly address. The assembly (10) also includes select logic (14) connected to receive the assembly address and operable to generate select signals based upon the assembly address. The select signals have a selected state and a not-selected state. A plurality of switches (18) are connected between the first plurality of terminals (20) and the integrated circuit device. The plurality of switches (18) are connected to receive the select signals. The switches (18) operate, when the select signals are in the selected state, to connect the first plurality of terminals (20) to the integrated circuit device.

Abstract: An integrated circuit device test arrangement includes a plurality of microcomputers. Each of the microcomputers is interconnected directly through a separate test socket to a separate integrated circuit device that is inserted into the test socket. A device tester is called to the plurality of microcomputers for transmitting information between the device tester and the plurality of microcomputers. Each microcomputer contains instructions and data for performing a test routine on the associated integrated circuit device and transmitting selected results of the test routine to the tester.

Abstract: A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.

Abstract: A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.