Abstract: A microcomputer architecture permits communication between a CPU and same-chip ports and input/output circuits to be carried only over a multiplexed address/data/interrupt bus, thereby permitting modified I/O hardware or other circuits to be included in the microcomputer without disturbing the CPU layout.

Abstract: A set of clock-controlled CMOS logic circuits employ a single pair of non-overlapping clocks controlling a set of transmission gates that have only a single pass transistor and a compensating non-standard threshold voltage in a portion of the logic gates.

Abstract: An integrated-circuit CPU saves layout space by employing the Address Register as the Extension Register for multiplication operations, the Address Register being modified to include shifting hardware.

Abstract: A microcomputer circuit is described for carrying out bit operations between registers and ports without the need for bit testing followed by branch operations. The microcomputer includes a bus (10) connected to provide communication to an ALU (22), registers (11, 12) and a serial port (13). A bit test circuit is connected to the bus (10) and provides a selected bit to a temporary carry storage (18) which in turn transfers the selected bit to a carry flag location (28a) within a status register (28). Instruction codes are input to an instruction register (32) which provides operating commands to an entry ROM (36) and an ALU control circuit (40). After a bit test operation is completed and in response to a copy or exchange instruction provided to the instruction register (32) a bit can be copied from one register to another register, bits can be exchanged between two registers or bits within a register can be parallel-to-serial converted and provided to the serial port (13).