Abstract: A method and apparatus is provided for logical steering of instructions or operations to avoid power related hot spots on a microprocessor. The instructions are distributed to one of multiple units located within different areas of the integrated circuit. Each of the multiple functional units are identical or perform substantially the same function in response to the instruction. Power dissipation is measured within each of the areas in which a functionally equivalent unit is located. If the power dissipation within an area exceeds a predetermined amount or value, a localized heating problem exists within the area. The instruction is dispatched or routed to one of the other functional units located within an area not experiencing a localized heating problem, thus reducing the possibility of catastrophic failure due to overheating, decreasing overall chip power dissipation, increasing chip reliability, and increasing throughput.

Abstract: A system for clocking self resetting CMOS (SRCMOS) circuits operating at high speed includes a clock generator circuit which produces a first pipeline clock pulse of relatively narrow width from a leading edge of a system clock having a relatively long duration with respect to the first pipeline clock, a number of delay circuits, the time duration of each of the delay circuits being determined by characteristics of evaluation logic in the SRCMOS circuits being clocked, the delay circuits being connected in a serial pipeline fashion such that each subsequent delayed clock pulse overlaps a preceding clock pulse by at least a predetermined minimum time duration. The clocking system also includes a cycle relax mode whereby the clock pulse output of the clock generator circuit may be extended for test or diagnostic purposes.