Abstract: A first phase locked loop has an oscillator operating at a first frequency and synchronized with a video signal. A counter in the first phase locked loop generates a plurality of timing signals. A second phase locked loop has an oscillator operating at a second frequency, less than the first frequency, and synchronized with a first one of the timing signals. A switch in a controller selects one of the first and second frequencies as an output. A memory for the video signal has a write clock input coupled to the slower oscillator, a read clock input coupled to the switch, and write and read reset inputs coupled respectively to second and third ones of the timing signals. The controller operates the switch responsive to an input signal. An analog to digital converter has a clamp signal input coupled to a fourth one of the timing signals.

Abstract: A television display system employing edge brightness flicker reduction by modulation of the vertical deflection signal has digital control words for modulation polarity (D) and magnitude (S). These digital words are coupled to an amplifier (900) and converted to a bipolar analog signal (Bp). The bipolar analog signal comprises values in a first and second range. Signals in the first range produce vertical deflection modulation in a first direction and signals in the second range produce vertical deflection modulation in the opposite direction.

Abstract: Video components U and V are applied to an input of a multiplexer. An output signal of the multiplexer is clamped using a clamper that is common for each of the video signal components. An input of the multiplexer is located upstream of the clamper. The clamped signal is processed through an analog-to-digital converter and applied to a line memory for providing video line doubling.

Abstract: A phase-lock-loop circuit for generating a clock signal at a frequency higher than a horizontal frequency of a video signal includes a phase detector. The phase detector includes a flip-flop that is set when a horizontal sync pulse occurs. An output of a counter that provides frequency division is decoded for resetting the flip-flop in each horizontal period. Other than for the flip-flop, and for the counting stages of the counter, only combinational logic components are used for producing a phase error indicative signal that is coupled via a low-pass filter to a control input of an oscillator of the phase-lock-loop circuit.

Abstract: In a remotely controlled power supply, a switching element has a main switching section coupled to an input voltage source and an on/off control section responsive to an on/off switching signal. A main power supply includes an input side which receives main power from the source when the main switching section is in the closed position and an output side for supplying power to loads. An on/off decoder decodes a command signal having a plurality of states including a run state and a standby state to provide the aforementioned on/off switching signal. A standby power supply is coupled to the input voltage source for providing standby power to the on/off decoder during standby, whereas the switching element disconnects the main power supply from the source during standby. A second decoder decodes the other states of the command signal. The two decoders may be provided with separate system clock generators that are operated asynchronously of each other.

Abstract: A teletext decoder includes a background or buffer memory operating as a first-in, first-out (FIFO) memory. The buffer memory is used for storing a large number of teletext pages. A given video line that contains teletext information is identified as such by the detection of part of a clock run-in sequence followed by the framing code. The video line is then stored in the background memory. After a user page request occurs, the background memory is read-out by a data processor operating in a full channel mode of operation for obtaining the information of the requested page. As long as the read-out operation has not been terminated, incoming teletext data is stored in the background memory. This enables teletext data received prior to termination of the read-out operation to be read out and processed by the data processor.

Abstract: The field rate of a video input signal is doubled by storing each field in a memory and recovering each stored fields twice so as to repeat each field and thus reduce flicker. To ensure that even fields overlay even fields, odd fields overlay odd fields and that all pairs of even and odd fields are interlaced, a timing unit provides a double field rate read control signal to the memory having a waveform that repeats on a two-field basis and supplies a double field rate vertical control signal to a vertical deflection generator having a waveform that is phase modulated and that repeats on a four-field basis. The vertical deflection generator has a constant retrace time and employs DC coupling, thereby avoiding raster shift which otherwise could occur as a result of the phase modulation.

Abstract: The field rate of a video input signal is doubled by storing each field in a memory and recovering each stored fields twice so as to repeat each field and thus reduce flicker. To ensure that even fields overlay even fields, odd fields overly odd fields and that all pairs of even and odd fields are interlaced, a timing unit provides a double field rate control signal to the memory having a waveform that repeats on a two-field basis and supplies a double field rate vertical synchronizing signal to a display having a waveform that repeats on a four-field basis. Registration of images is enhanced further by means of a vertical scan generator having a constant retrace time, a fixed retrace level and employing DC coupling thereby avoiding raster shift which otherwise could occur as a result of the use of non-equidistant vertical synchronizing pulses.

Abstract: A digital video signal processing system is described wherein analog video signal is sampled by a sampling clock phase locked to burst and the digital video samples are processed with a clock phase locked to horizontal sync. The respective sampling phases of the sampling clock are encoded and concatenated with the digital video samples for purposes of synchronously demodulating the color difference signals of composite video. Burst clock to line locked clock sample conversion is accomplished in a FIFO memory.

Abstract: A frequency and phase control circuit for a television receiver comprises a first phase detector for adjusting the frequency of the horizontal oscillator in response to horizontal sync pulses. A second phase detector maintains a predetermined phase relationship between the deflection circuit switching signals and a pulse indicative of the amplitude zero crossing of the horizontal deflection current. The zero crossing signal is derived from a transformer in series with the horizontal deflection winding. The transformer is normally magnetically saturated by the deflection current, except when the deflection current amplitude is close to zero. A voltage is then developed across the transformer secondary windings, producing the zero crossing pulse.

Abstract: In a television display system, a deflection yoke is placed over the neck of a cathode ray tube to generate a raster by means of simultaneous horizontal and vertical sweep of the electron beams. A picture, derived from information contained in the composite video signal produced by the signal processing circuits, is displayed on the screen of the cathode ray tube. In the horizontal deflection circuit portion of the television display system, a trace capacitor is coupled to a deflection winding. A trace switch, responsive to a deflection rate signal that is synchronized with the composite video signal, periodically applies to the deflection winding the voltage developed across the trace capacitor to generate raster scanning current in the deflection winding during a deflection cycle. The losses incurred during a deflection cycle tend to produce a scanning current waveform that introduces asymmetrical linearity distortion to the picture display.

Abstract: A linearity inductance and a side pincushion correction inductance are wound on outer leg core portions of a single E-core. A magnet biases the linearity inductance core portion for saturating that portion each horizontal deflection cycle for producing a linearity corrected horizontal deflection current. A high reluctance path for flux mutually linking both the linearity and side pincushion correction windings is provided by the E-core configuration. The portion of the flux generated by the side pincushion correction winding that does flow in the linearity winding core portion compensates for undesirable vertical rate changes in the magnetic bias of the linearity winding core portion.

Abstract: A synchronous switched vertical deflection (SSVD) circuit is coupled by a flyback transformer to a horizontal deflection circuit. The SSVD circuit loads the horizontal deflection circuit at a vertical parabolic rate providing East-West pincushion correction. Because of the inductance of the vertical deflection winding, the parabolic loading is asymmetrical, producing a keystone-like raster distortion. A correction circuit, such as a constant current source coupled to the vertical deflection winding, substantially reduces the asymmetry of the loading thereby substantially reducing the keystone-like distortion.

Abstract: A kinescope deflection arrangement includes a deflection winding driven by a deflection generator. A pincushion correction circuit includes a switchable impedance coupled in series with the deflection winding. A portion of the retrace voltage pulse appears across the switchable impedance. A transformer has a primary winding coupled to the output of the deflection generator, and a secondary winding on which a sample of the retrace pulse appears. A pincushion correction circuit damping resistor is coupled between the transformer secondary winding and the impedance.

Abstract: A side pincushion correction circuit includes an impedance circuit coupled in series with the horizontal deflection coil. A switch coupled across at least a part of the impedance circuit is closed at a time during the retrace interval which is progressively advanced during a first portion of the horizontal retrace interval and progressively retarded during a second portion. Damping of the impedance circuit is provided by a second switch operated at a rate synchronous with the first. The second switch is coupled between a point of the impedance circuit and a voltage source.

Abstract: A horizontal deflection circuit drives a voltage generator by way of a first transformer, and also drives a switched synchronous vertical deflection circuit. In order to reduce variations of the energy coupled from the horizontal deflection circuit to the vertical deflection circuit attributable to variation of the load coupled to the voltage generator, the horizontal deflection circuit is coupled to the vertical deflection circuit by second transformer means separate from the first.

Abstract: A source of alternating current in a power supply and deflection system of a television receiver is coupled to a primary winding of a transformer, a relatively closely coupled secondary winding of which provides a voltage which may be rectified for providing operating voltage for another portion of the receiver such as the vertical deflection system. Yet another portion of the receiver, such as the audio section, is energized by voltage derived from a winding so disposed around the transformer as to be energized by leakage flux from the transformer for substantially reducing the effects of variations of the audio loading on the deflection systems.

Abstract: A switching regulator power supply which provides operating voltage for a deflection system which in turn provides the ultor voltage for a picture tube and which ultor voltage is subject to variation caused by picture tube beam loading is controlled by a single pulse, the timing of which synchronizes the regulator operation and the width of which is determined by a bias level on a transistor which is coupled to a pulse differentiating network, the bias being determined by the level of an ultor voltage representative signal.

Abstract: A switching regulator adapted to be coupled to a source of alternating current potential produces a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition. A modulator coupled to a synchronized oscillator produces a synchronized control signal having an amplitude proportional to the amplitude of the direct current potential. A drive signal generator coupled to the modulator and the switching regulator produces a first drive signal condition having a duration relative to the duration of the second drive signal condition which is proportional to the amplitude of the control signal, thereby providing for regulation of the direct current potential.

Abstract: A gating circuit for a deflection system which includes a first switch which is coupled to a deflection winding for supplying energy to the deflection winding during a trace interval of each deflection cycle. A commutating network including a second switch is coupled to the deflection winding and supplies energy to the deflection winding during a commutating interval of each deflection cycle. A coupling network couples a first polarity portion of gating signals developed by the commutating network to the first switch during the trace interval to enable conduction of the first switch. The coupling network also provides a second polarity portion of the gating signals to the first switch during the commutating interval to enable the turn off of the first switch.