Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: A MOSFET transistor having silicide formed on top of a polysilicon gate conductor, on partially exposed sidewalls of the polysilicon gate conductor, and on junction regions in an underlying semiconductor substrate is provided. Opposed sidewalls of the polysilicon gate conductor are surrounded by dielectric sidewall spacers. An upper surface of the dielectric spacers is lower than an upper surface of the polysilicon gate conductor thereby exposing a portion of the sidewall surfaces of the polysilicon gate conductor. A substantial portion of the polysilicon gate conductor, including the top of the gate and the exposed portion of the sidewall surfaces, may then be subjected to a salicidation process. During this process, salicide structures are also formed on the junctions regions. Therefore, silicide may be simultaneously formed on a substantial portion of the polysilicon gate and on junctions regions providing a gate with lower resistivity without consuming the junction regions during salicidation.