Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

Abstract: A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

Abstract: A method includes detecting an occurrence of an event associated with a memory sub-system comprising blocks of non-volatile memory cells. The method further includes responsive to detecting the occurrence of the event, providing signaling to disable at least a portion of the memory sub-system, an interface coupled to the memory sub-system, or both.

Abstract: A method includes identifying a target plane in respective planes of a memory die in a non-volatile memory array and identifying, from blocks of non-volatile memory cells coupled to a common bit line in the target plane, at least one target block in the target plane. The method further includes performing an operation to disable at least one gate associated with the at least one target block to prevent access to the blocks of non-volatile memory cells coupled to the common bit line in the target plane.

Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.

Abstract: A system includes a first memory device including a non-volatile memory device, a second memory device and a processing device, operatively coupled with the first memory device and the second memory device, to perform operations including configuring a system in accordance with a configuration designating an interface standard for exposing a storage element implemented on the first memory device to a first protocol of the interface standard and a persistent memory region (PMR) implemented on the second memory device to a second protocol of the interface standard, and performing at least one system operation based on the configuration.

Abstract: A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

Abstract: In an example, an apparatus may include a memory comprising a number of groups of memory cells and a controller coupled to the memory and configured to track respective invalidation velocities of the number of groups of memory cells and to assign categories to the number of groups of memory cells based on the invalidation velocities.

Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

Abstract: Systems and methods for allocation of overprovisioned blocks for minimizing write amplification in solid state drives are disclosed. An example system comprises: a plurality of memory devices and a processing device operatively coupled to the memory devices, the controller configured to: determine a value of a data stream attribute associated with a data stream; determine, based on the value of the data stream attribute, an overprovisioning factor associated with the data stream, wherein the overprovisioning factor is calculated to provide a uniform distribution of valid translation unit counts (VTCs) across the data stream; and allocate, based on the overprovisioning factor, a plurality of overprovisioned blocks to the data stream.

Abstract: A method for managing garbage collection in a memory subsystem, where a stream data manager writes data units from a stream of data into an allocated portion of memory composed of a plurality of blocks. The stream data manager evaluates a behavior of the stream of data to calculate the stream's efficiency, where the efficiency value is calculated based on an amount of invalid data units stored in the allocated portion of memory. The stream data manager determines a threshold of valid data units in a block within the allocated portion of memory, applicable to each block in the plurality of blocks for determining when to perform garbage collection. The stream data manager performs the garbage collection of a first block of the plurality of blocks in response to determining that a value of valid data units in the first block is within a predetermined range of the threshold value.

Abstract: A host command is received to configure a system to have a configuration designating an interface standard for exposing a storage element and a persistent memory region (PMR). The storage element is visible to a first protocol of the interface standard and the PMR is visible to a second protocol of the interface standard. The storage element is implemented on a first memory device of the system including a non-volatile memory device and the PMR is implemented on a second memory device of the system. The system is configured in accordance with the configuration.

Abstract: A memory component includes multiple fuses, a memory array having a multiple blocks, and control logic operatively coupled with the memory array and the plurality of fuses. The control logic is to perform operations including detecting a failure to completely erase a block of the plurality of blocks in response to an attempted erasure of the block; receiving a blow fuse command in response to the failure to completely erase the block; and blowing a fuse, of the plurality of fuses, coupled with the block, to make the block electrically inaccessible to the control logic in response to receipt of the blow fuse command.