Patents by Inventor William B. Glendinning

Patent number: 4816361
Abstract: A layer of metal is deposited on a mask substrate and then covered with a layer of negative electron resist. A delineation of the peripheral boundaries of the desired mask geometry is carried out by means of a direct-write electron beam. After development and etching, the peripherally defined metal boundaries are all that remain on the substrate. The substrate is then covered with a positive electron resist. The mask is, next, raster scanned with a low intensity beam until a boundary is detected and then the beam intensity is increased significantly to a level sufficient to expose the positive resist. The scan and exposure continue until the mating peripheral boundary is detected and then the beam is rapidly decreased in intensity to its former low detection level. The positive resist subjected to the exposure level beam intensity is removed and a layer of metal is evaporated over the entire mask substrate.
Type: Grant
Filed: November 27, 1987
Issued: March 28, 1989
Assignee: The United States of America as represented by the Secretary of the Army
Inventor: William B. Glendinning
Patent number: 4797334
Abstract: A layer of metal is deposited on a mask substrate and then covered with a layer of positive electron resist. A delineation of the peripheral boundaries of the desired mask geometry is carried out by means of a direct-write electron beam. Development and etching steps serve to remove the positive resist and the underlying metal in the beam-exposed peripheral boundaries. The mask is then raster scanned with a low intensity beam until a boundary is detected and then the beam intensity is increased significantly to a level sufficient to expose the positive resist. The scan and exposure continue until the mating peripheral boundary is detected and then the beam is rapidly decreased in intensity to its former low intensity level. The substrate is next developed to remove the positive resist subjected to the increased exposure-level beam intensity; and, the metal underlying this positive resist is then etched away.
Type: Grant
Filed: December 14, 1987
Issued: January 10, 1989
Assignee: The United States of America as represented by the Secretary of the Army
Inventor: William B. Glendinning
Patent number: 4761560
Abstract: A test pattern which is applied to a wafer or mask by electron beam lithophy for measuring proximity effects. The pattern comprises two lines which intersect at a small angle, for example 1.degree. so that the proximity effects of the two lines combine within the angle to displace the angle vertex by an amount much larger than the proximity effect of an isolated line. A calibration scale is provided to measure this enhanced proximity effect by viewing the pattern with an optical microscope.
Type: Grant
Filed: January 25, 1984
Issued: August 2, 1988
Assignee: The United States of America as represented by the Secretary of the Army
Inventor: William B. Glendinning
Patent number: 4610948
Abstract: Silicon wafers are imprinted with microelectronic circuit patterns by first ithographing the outlines or peripheries of all circuit features of a given wafer level by means of a narrow line formed by direct-writing electron beam lithography utilizing a positive electron resist, then using proximity photoprinting to complete the lithography of that level using a positive photoresist and a photomask with oversized opaque areas so that the pattern edges on the wafer exposed to the flux passing through the photomask will fall within the peripheral lines formed by the electron beam.
Type: Grant
Filed: January 25, 1984
Issued: September 9, 1986
Assignee: The United States of America as represented by the Secretary of the Army
Inventor: William B. Glendinning
Patent number: 4194187
Abstract: A relatively high speed analog-to-digital converter is a charged coupled ice preferably formed as a metal-oxide semiconductor integrated circuit. It includes a pair of potential charge packet wells, an electrode gate to control the transfer of charge packets in a seesaw manner between the two wells, electrode gates to control the dissipation of charges from the wells to sinks, electrode gates to control the input of a charge representing an analog signal to one of the wells, electrode gates to control the detection of charge packets, a clock and a logic control to operate the electrode gates in a predetermined sequence.
Type: Grant
Filed: August 7, 1978
Issued: March 18, 1980
Assignee: The United States of America as represented by the Secretary of the Army
Inventor: William B. Glendinning
Patent number: 4105805
Abstract: A layer of silicon nitride (Si.sub.3 N.sub.4) is deposited on a silicon substrate. A mask provided with windows representing device structures is then formed over the silicon nitride layer. Oxygen is then implanted through the window portion of the silicon nitride layer into the Si.sub.3 N.sub.4 /Si interface region to form a tunneling insulator interface layer of silicon dioxide (SiO.sub.2). The final structure is heat treated and then has the form Si.sub.3 N.sub.4 /SiO.sub.2 /Si. It can be made into a metal nitride oxide semiconductor (MNOS) field effect transistor device by conventional diffusion, ion implant and metallization processes.
Type: Grant
Filed: December 29, 1976
Issued: August 8, 1978
Assignee: The United States of America as represented by the Secretary of the Army
Inventors: William B. Glendinning, Albert Mark