Abstract: An inter-wound spiral center tapped inductor includes a first and second spiral inductor trace arranged in a plane in an inter-nested pattern with a center tap connection. The inter-wound traces implement the two halves of a center-tapped inductor over a common area to provide a practical inductor element for use in balanced and differential circuits.

Abstract: A bit synchronizer capable of operation over all frequencies, limited only by the speed of the integrated circuits and other components. The input data can be any random antipodal data. A programmable scaling circuit allows the operator to select the desired half octave range of operation. Half octaves can be scanned automatically by the autorange feature of the invention. An acquisition circuit sweeps over the selected half octave, diverting frequency correction pulses in order to sweep a voltage controlled oscillator (VCO). Lock is recognized when a preselected number of data transitions with phase error below a preset maximum occur consecutively. A second order phase lock loop (PLL) provides both phase and frequency correction.

Abstract: A partly analog partly digital bit synchronizer capable of acquisition and operation over an arbitrarily broad range of data rates is disclosed. A second order phase lock loop (PLL) is employed providing both phase and frequency correction to a voltage controlled oscillator (VCO). The phase detector consists of a binary counter whose most significant bit (MSB) is defined to be the recovered clock. The desired data transition points are defined as coinciding with the falling edge of the counter's MSB. At each data transition, the least significant bits within the counter are used to set the duration of phase and frequency correction pulses proportional to the phase error, which pulses are then fed to the VCO. An acquisition circuit diverts the frequency correction pulses in order to sweep the VCO within a selected half octave. Lock is recognized when a preselected number of data transitions with phase error below a preset maximum occur consecutively.