Abstract: A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

Abstract: A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.

Abstract: An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).

Abstract: A data processing system and a method for performing dynamic bus signal termination uses a dynamic bus termination circuitry (14 or 16) with a device (10 or 12). The circuitry is enabled when data is incoming to the device and is disabled when data is outgoing from the device to selectively reduce unwanted signal reflection at the signal end of a bi-directional bus (17). The disabling allows the circuitry to be removed or tristated from any connection with the bus (17) when not needed (i.e., data outgoing) to reduce loading. The disabling of the termination circuitry also aids in reducing the power consumption of the part when either the bus is sitting idle or the part is in a low power mode of operation.

Abstract: An integrated circuit implements an on chip thermal circuit (12) for measuring temperature of an operating integrated circuit die (10) by requiring only one dedicated integrated circuit pin (16). A second integrated circuit pin (18) is utilized but is also connected directly connected to other circuitry (14) on the integrated circuit and is used by the other circuitry at the same time that the integrated circuit die temperature is being measured. In one form, the second integrated circuit pin is a ground terminal. Error voltages coupled to the ground terminal may be removed from the temperature calculation by an external differential amplifier (24).

Abstract: A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefetch controller in the IPU keeps the instruction stream prefetched so that the instruction queue may load any combination of one, two, or three word instructions into the pipelined instruction unit every clock cycle. The pipelined instruction unit receives instruction words from the instruction queue, and decodes the instruction for execution operations, and for the instruction length/pipeline movement. A queue filling method is provided for maintaining the requisite number of instruction words in the instruction queue to avoid pipeline stalls. The queue filling method is based upon the movement of the instruction pipeline attributable to the usage by an instruction sequencer of the instruction words received from the instruction queue.

Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Abstract: A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selected for replacement are marked dirty, the cache controller "pushes" the cache line or dirty portions thereof into a buffer, which stores the cache line pending completion, by a bus interface controller, or the burst line read. When the burst line read terminates abnormally, due to a bus error or bus cache inhibit (or any other reason), the data cache controller reloads the copy-back cache with the cache line stored in the buffer. The reloading of the copy-back cache avoids the potential for multiple concurrent exception conditions, and eliminates the problem of unnecessarily removing an otherwise valid cache entry from the cache.

Abstract: A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allows the programmer to fully utilize the maximum bus bandwidth of the system bus for memory to memory transfers of data (e.g. DMA, block moves, memory page initialization) and transfers of instructions/data to detached coprocessors.

Abstract: A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance then the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Abstract: A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a tag address, and a mixed size status field. The mixed size status fields provide one bit to indicate the validity of the data cache entry and multiple bits to indicate if the entry contains data that has not been written to memory (dirtiness). Multiple dirty bits provide a data cache controller with sufficient information to minimize the number of memory accesses used to unload a dirty entry. The data cache controller uses the multiple dirty bits to determine the quantity and type of accesses required to write the dirty data to memory. The portions of the entry being replaced that are clean (unmodified) are not written to memory.

Abstract: A data processing system having a mechanism for changing communication bus mastership when a series of locked operand transfer sequences are executed. The system has at least two processors coupled via the communication bus and a bus arbiter. In one form, a locked transfer end signal is provided by each processor to the bus arbiter so that if a high priority need is recognized by the bus arbiter during early execution of a plurality of locked operand transfer sequences the high priority need can be responded to by the bus arbiter before completion of all of the locked sequences. In another form, control signals are provided by the bus arbiter to each processor to accomplish the equivalent function.

Abstract: A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory read operation, and simultaneously invalidate `dirty` or altered data from the write-back cache. The method minimizes the number of cache accesses required to maintain coherency between the cache and main memory during page-out/page-in sequences initiated by the alternate bus master, thereby improving system performance.

Abstract: A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division multiplexed with data bits when both are written to external circuitry. In a second or normal mode, the circuit's address and data terminals are not connected and address bits are communicated with the circuit independent of data bits which are communicated with the circuit. No circuitry external to the integrated circuit is required to implement the multiplexed mode. A control portion insures that bit collisions are avoided when the circuit is in the multiplexed mode.

Abstract: A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed.