Patents by Inventor William B. Mraz
William B. Mraz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7446388Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: November 21, 2005Date of Patent: November 4, 2008Assignee: UltraSource, Inc.Inventors: Michael D. Casper, William B. Mraz
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Patent number: 7425877Abstract: A system and method for the fabrication of high reliability high performance Lange couplers (optionally including capacitors (1011), inductors (1012), multi-layer interconnects (1013), and resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed Lange coupler method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: March 26, 2005Date of Patent: September 16, 2008Assignee: UltraSource, Inc.Inventors: Michael D. Casper, William B. Mraz
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Patent number: 7327582Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: March 18, 2005Date of Patent: February 5, 2008Assignee: UltraSource, Inc.Inventors: Michael D. Casper, William B. Mraz
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Patent number: 6998696Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: October 15, 2003Date of Patent: February 14, 2006Inventors: Michael D. Casper, William B. Mraz
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Patent number: 6890629Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: October 15, 2003Date of Patent: May 10, 2005Inventors: Michael D. Casper, William B. Mraz
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Patent number: 6761963Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: GrantFiled: September 21, 2001Date of Patent: July 13, 2004Inventors: Michael D. Casper, William B. Mraz
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Publication number: 20040081811Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: ApplicationFiled: October 15, 2003Publication date: April 29, 2004Inventors: Michael D. Casper, William B. Mraz
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Publication number: 20040080021Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: ApplicationFiled: October 15, 2003Publication date: April 29, 2004Inventors: Michael D. Casper, William B. Mraz
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Publication number: 20020089810Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).Type: ApplicationFiled: September 21, 2001Publication date: July 11, 2002Inventors: Michael D. Casper, William B. Mraz
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Patent number: 5806856Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.Type: GrantFiled: November 21, 1996Date of Patent: September 15, 1998Assignee: Ferrofluidics CorporationInventors: Thomas J. Black, Jr., William B. Mraz
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Patent number: 5593164Abstract: A ferrofluidic seal is fitted with a centering ring having an inner edge adapted for engagement with a rotating shaft for centering the seal about the rotating shaft. The centering ring automatically engages the shaft and centers the seal when the seal is fitted onto the shaft. The centering ring is affixed to the housing, and/or magnet and pole module. In one embodiment, the centering ring may be removed after it performs its centering function. In another embodiment, the centering ring is non-removable and remains within the seal permanently. According to this latter embodiment, the centering ring serves the additional purpose of retaining ferrofluid, expelled from the seal during "bursting", within magnetic reach of the seal so as to be re-drawn into the seal, thus extending seal life. Additionally, a ferrofluid retaining ring absent a centering function may be employed.Type: GrantFiled: November 22, 1995Date of Patent: January 14, 1997Assignee: Ferrofluidics CorporationInventors: William B. Mraz, Thomas J. Black, Jr., Paul E. McMahan, Larry A. Hufford, David T. Mooney, Robert C. Watkins
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Patent number: 5560620Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.Type: GrantFiled: June 7, 1995Date of Patent: October 1, 1996Assignee: Ferrofluidics CorporationInventors: Thomas J. Black, Jr., William B. Mraz
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Patent number: 5474302Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.Type: GrantFiled: August 27, 1992Date of Patent: December 12, 1995Assignee: Ferrofluidics CorporationInventors: Thomas J. Black, Jr., William B. Mraz