Patents by Inventor William B. Mraz

William B. Mraz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7446388
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: November 4, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 7425877
    Abstract: A system and method for the fabrication of high reliability high performance Lange couplers (optionally including capacitors (1011), inductors (1012), multi-layer interconnects (1013), and resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed Lange coupler method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: March 26, 2005
    Date of Patent: September 16, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 7327582
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: February 5, 2008
    Assignee: UltraSource, Inc.
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6998696
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: February 14, 2006
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6890629
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: May 10, 2005
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 6761963
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: July 13, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Publication number: 20040081811
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Publication number: 20040080021
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Application
    Filed: October 15, 2003
    Publication date: April 29, 2004
    Inventors: Michael D. Casper, William B. Mraz
  • Publication number: 20020089810
    Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).
    Type: Application
    Filed: September 21, 2001
    Publication date: July 11, 2002
    Inventors: Michael D. Casper, William B. Mraz
  • Patent number: 5806856
    Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: September 15, 1998
    Assignee: Ferrofluidics Corporation
    Inventors: Thomas J. Black, Jr., William B. Mraz
  • Patent number: 5593164
    Abstract: A ferrofluidic seal is fitted with a centering ring having an inner edge adapted for engagement with a rotating shaft for centering the seal about the rotating shaft. The centering ring automatically engages the shaft and centers the seal when the seal is fitted onto the shaft. The centering ring is affixed to the housing, and/or magnet and pole module. In one embodiment, the centering ring may be removed after it performs its centering function. In another embodiment, the centering ring is non-removable and remains within the seal permanently. According to this latter embodiment, the centering ring serves the additional purpose of retaining ferrofluid, expelled from the seal during "bursting", within magnetic reach of the seal so as to be re-drawn into the seal, thus extending seal life. Additionally, a ferrofluid retaining ring absent a centering function may be employed.
    Type: Grant
    Filed: November 22, 1995
    Date of Patent: January 14, 1997
    Assignee: Ferrofluidics Corporation
    Inventors: William B. Mraz, Thomas J. Black, Jr., Paul E. McMahan, Larry A. Hufford, David T. Mooney, Robert C. Watkins
  • Patent number: 5560620
    Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 1, 1996
    Assignee: Ferrofluidics Corporation
    Inventors: Thomas J. Black, Jr., William B. Mraz
  • Patent number: 5474302
    Abstract: An on-site fillable ferrofluidic seal comprises a ferrofluidic seal having at least one ferrofluid conducting channel extending through either the magnet, through one of the pole pieces which sandwich the opposing pole ends of the magnet, or through both the magnet and a pole piece. The conducting channel extends to a location where deposited ferrofluid will be drawn to the gaps between the pole pieces and the shaft. In another embodiment a multi-stage seal is filled by displacing the pole piece/magnet assembly axially relative to the shaft so that each pole piece projection falls halfway axially between two shaft projections. The displacement alters the normal magnetic field pattern to create a substantially uniform magnetic field throughout the pole piece/shaft interface region such that ferrofluid can be drawn through the region.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: December 12, 1995
    Assignee: Ferrofluidics Corporation
    Inventors: Thomas J. Black, Jr., William B. Mraz