Abstract: A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.

Abstract: A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.