Patents by Inventor William C. Dunn

William C. Dunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sense line coupling reduction system
    Patent number: 3942164
    Abstract: The inductive and capacitive coupling between adjacent sense lines in a semi-conductor memory is minimized by periodically interchanging the locations of the two sense lines assigned to each column of storage cells in a semi-conductor memory.
    Type: Grant
    Filed: January 30, 1975
    Date of Patent: March 2, 1976
    Assignee: Semi, Inc.
    Inventor: William C. Dunn
  • Sense line balancing circuit
    Patent number: 3936810
    Abstract: In semiconductor memory cells of the type including flip flop circuits in each cell and two sense output lines for determining the binary bits stored in the cell, an attempt to read data stored in the cell after a previous operation, before the sense lines have been fully restored to their quiescent state can result in the loss of data. This invention provides a means for restoring the sense lines very rapidly after an operation so that loss of data is prevented and the memory may be accessed at a higher frequency.
    Type: Grant
    Filed: January 20, 1975
    Date of Patent: February 3, 1976
    Assignee: Semi, Inc.
    Inventor: William C. Dunn