Abstract: A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller a piori know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgement for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgement for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller a piori know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A method and system for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. A system controller provides dedicated transaction request queues and controls the forwarding of transactions from a processor to a slave. The transaction requests are automatically forwarded to an intended slave on the same address bus as the system controller immediately. The system controller determines whether the proper criteria are met for that slave to receive such a request, such as the slave's request receive queue is not full and that global ordering requirements are met. If so, then on a separately provided line, the system controller validates the request for immediate reception by the slave.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet. and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.

Abstract: This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.

Abstract: A system for resolving packet errors and busy acknowledgments for packets in a ring network, to maintain continued packet distribution on the network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: A method and apparatus for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. An interconnect system controller provides dedicated transaction request queues for master interfaces and controls the forwarding of transactions to slave interfaces. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. An acknowledgement from a downstream queue indicates to the sender that there is space in it for another transaction. Accelerated processing of transaction requests from a processor to a slave device on its local address bus is achieved by immediately forwarding the request to the slave device while determining the validity of the request for that slave, including whether the slave's input queue can accept it.

Abstract: A dynamically reconfigurable hybrid computer system is provided that executes transaction requests in one of two ways--either as packet-switched transactions or as circuit-switched transactions. Each transaction request is inspected as it is issued by a master device in the system, and it is determined in each case whether the transaction should be executed as a packet-switched transaction or as a circuit-switched transaction. Preferably, all slave read requests in a uniprocessor system are executed as circuit-switched transactions, such that a system controller coupled between the master device and the slave device, upon receipt of the request, immediately schedules the datapath between the master and slave devices and suspends other, competing transactions to execute the data transfer. The states of other transactions are stored, and are restored upon completion of the circuit-switched transaction.