Abstract: A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive. Upon the identification of a consecutive address sequence, the succession of real addresses are generated directly by a counter. The memory of the computer system is partitioned into odd and even banks which are selectively addressed using the odd and even segments of the address generated in the counter. Output data from each memory bank is stored in a corresponding register operable to transmit the data entered therein during a previous memory address cycle while the anticipated next address data is written into the other register. The prefetch architecture may be meaningfully used to accelerate the access rate of a memory shared by multiple processors.

Abstract: A data processing system includes a plurality of data handling subsystems which communicate with each other by means of an interval transfer bus. The subsystems are located at ports along the bus and each is provided with a local bus adapter interconnecting the subsystem with the bus. Busy lines are provided, one for each port on the bus, and all such busy lines are connected to all of the ports for use by any such port when the latter is acting as a source. Each busy line is uniquely connected to an individual one of the ports and is employed at such individual port to signal to all other ports the busy or available state of the individual port. A subsystem, acting as a source, inspects the busy line that is unique to the selected destination, and if availability of the selected destination subsystem is indicated by the state of its busy line, a request for access is issued by the source, and if granted, the source raises the distination busy line to busy state, and transmits its message.