Abstract: An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.

Abstract: A lighting source that can be deployed in a hazardous environment is disclosed. For example, the lighting source comprises at least one light emitting diode and a power supply for providing power to the at least one light emitting diode. The lighting source also comprises an enclosure for housing the at least one light emitting diode and the power supply, where said lighting source is for deployment in a hazardous environment.

Abstract: A lighting source that can be deployed in a hazardous environment is disclosed. For example, the lighting source comprises at least one light emitting diode and a power supply for providing power to the at least one light emitting diode. The lighting source also comprises an enclosure for housing the at least one light emitting diode and the power supply, where said lighting source is for deployment in a hazardous environment.

Abstract: A method and apparatus for providing a luminaire employing at least one Light Emitting Diode (LED) device as the light source and a metal beverage container as the luminaire housing.

Abstract: An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this state the two architected registers alias to one physical register. When the source register of the Load Address instruction is specified as the target address of a subsequent instruction, a free physical register is assigned to the Load Registers source register. And with this assignment the alias is thus broken. Similarly when the target register of the Load Address instruction is the target address of a subsequent instruction, a new physical register is assigned to the Load Registers target address. And with this assignment the alias is thus broken.

Abstract: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

Abstract: A method of operating an arithmetic logic unit (ALU) by inverting a result of an operation to be executed during a current cycle in response to control signals from instruction decode logic which indicate that a later operation will require a complement of the result, wherein the result is inverted during the current cycle. The later operation may be a subtraction operation that immediately follows the first operation. The later instruction is decoded prior to the current cycle to control the inversion in the ALU. The ALU includes an adder, a rotator, and a data manipulation unit which invert the result during the current cycle in response to an invert control signal. The second operation subtracts the result during a subsequent cycle in which a carry control signal to the adder is enabled, and the rotator and the data manipulation unit are disabled. The ALU may be used in an execution unit of a microprocessor, such as a fixed-point unit.

Abstract: A fire retardant barrier panel (16) comprising a first protective layer (18) of a first material and a fire resistant phenolic-based resin layer (19) bonded to the protective layer. The first material may be selected from the group consisting of gypsum, ceramic fiber, phenolic foam, basalt, fiberglass, carbon fiber, mineral wool and intumescent materials. The resin may be a phenol or phenolic resin. The fire retardant barrier panel may further comprise a second protective layer (20) bonded to the resin layer (19) such that the resin layer is between the first and second protective layers. The second protective layer (20) may be selected from the group consisting of gypsum, ceramic fiber, phenolic foam, basalt, fiberglass, carbon fiber, mineral wool and intumescent materials.

Abstract: A more efficient method of handling instructions in a computer processor, by associating resource fields with respective program instructions wherein the resource fields indicate which of the processor hardware resources are required to carry out the program instructions, calculating resource requirements for merging two or more program instructions based on their resource fields, and determining resource availability for simultaneously executing the merged program instructions based on the calculated resource requirements. Resource vectors indicative of the required resource may be encoded into the resource fields, and the resource fields decoded at a later stage to derive the resource vectors. The resource fields can be stored in the instruction cache associated with the respective program instructions. The processor may operate in a simultaneous multithreading mode with different program instructions being part of different hardware threads.

Abstract: Novel protected cyclopeptide intermediates are prepared from polymyxin B are used to synthesize new peptide antibiotics. Intermediates are readily derivatized and deprotected to provide new families of antibiotics, which have potent anti-bacterial activity against gram-negative bacteria; but also are useful and potent against gram-positive bacteria.

Abstract: A method for controlling the delivery of vapor from a bubbler containing a supply of chemical fluid through which a carrier gas is bubbled and from which bubbler vapors are delivered in a vapor stream entrained with the carrier gas. In general, the method involves equilibrating the pressure within the head space to that of the chemical fluid fill line to maintain a constant fluid level based on pressure and not relying on conventional level sensors and controllers.

Abstract: The present invention provides derivatives of lipopeptide antibiotics that display antimicrobial activity against microorganisms, methods and compounds for synthesizing such antimicrobial derivatives and analogues, and methods of using the compounds in a variety of contexts, including in the treatment and prevention of microbial infections.

Abstract: A domino CMOS circuit has a number of domino gates, a common virtual ground node and a common evaluation NFET device. Each domino gate provides a PFET precharge device, an NFET device tree, an output inverter stage, a dynamic node, a plurality of input nodes, a clock input node and an output node. The PFET precharge device is coupled to a high voltage supply rail, the clock input node and the dynamic node and an NFET device tree is coupled to the common virtual ground node, to the plurality of inputs and to the dynamic node. An output inverter stage is coupled to the high voltage supply rail, to said dynamic node, to a low voltage supply rail and to said output node. And for improving performance, a common evaluation NFET device is coupled to said clock inputnode, to the to said low voltage supply rail and to the common virtual ground node. The virtual ground node is coupled to the low voltage supply rail when a high voltage is applied to clock input node.

Abstract: Improved memory access is provided for use when addressing dynamic random access modules (DRAMs). Both the memory contoller and the main memory hardware remember the row address of the last access. The main memory hardware redrives that row address to the DRAMs after completion of an access.

Abstract: A state machine computing system provides multiple state registers, a recursive hardware state machine computing system; particularly address translation hardware which can be used in multiprocessors, parallel machines and massively parallel machines. The hardware state machine includes a mechanism to push values into a state register stack and to pop values from the state register stack. The stack consists of a plurality of state registers, one of which is designated the current state register and the remainder designated as prior (or saved) state registers. Recursive logic is provided to increment the current state register. The recursive state machine described provides significant advantages over prior art hardware implementations of guest virtual address translation because guest virtual address translations recursively invoke host virtual address translation.