Abstract: An automated order fulfillment system and mobile robot are disclosed, where the mobile robot includes a compliant drive for moving between levels of a multilevel storage structure. In one example, the compliant drive comprises a drive shaft having splines configured to provide rotational play that prevents jamming of a vertical drive gear on the end of the shaft with a rack in a vertical track.

Abstract: An analog-to-digital conversion system has an analog-to-digital converter and a digital-filter system. The digital-filter system is connected to the output of the analog-to-digital converter. A processor is connected to the output of the digital-filter system so that the processor transparently receives filtered sample data in the native format of the analog-to-digital converter. An FIR filter circuit in the digital-filter system is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit connected between the analog-to-digital converter and the processor. A configuration and control-register circuit is connected to the circuit for sample collection and data-type conversion, and to the FIR filter circuit, for selectively controlling the operation of the digital filter system according to parameters for data conversion and filter operation passed to the configuration and control-register circuit over a serial interface.

Abstract: An analog-to-digital conversion system has an analog-to-digital converter and a digital-filter system. The digital-filter system is connected to the output of the analog-to-digital converter. A processor is connected to the output of the digital-filter system so that the processor transparently receives filtered sample data in the native format of the analog-to-digital converter. An FIR filter circuit in the digital-filter system is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit connected between the analog-to-digital converter and the processor. A configuration and control-register circuit is connected to the circuit for sample collection and data-type conversion, and to the FIR filter circuit, for selectively controlling the operation of the digital filter system according to parameters for data conversion and filter operation passed to the configuration and control-register circuit over a serial interface.

Abstract: We disclose a CIC digital filter having an arbitrary-integer decimation rate. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. Sequentially-connected integrator functions are connected to the shifter (or multiplier); a decimation function receives input from the integrator functions; and sequentially-connected differentiator functions receive input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value.

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal.

Abstract: A system includes an integrated circuit device that compares the relative phase of first and second signals to a very high precision. The system includes a first input for receiving the first signal with a first edge, and a second input for receiving the second signal with a second edge. A first delay chain includes a first at least one delay element, and the first signal is delayed across the first at least one delay element, each of the first at least one delay element includes an output tap. A second delay chain includes a second at least one delay element, the second signal is delayed across the second at least one delay element, each of the second at least one delay element includes an output tap.

Abstract: A system includes a signal reconstruction controller (110) electrically coupled to at least one analog-to-digital converter (ADC) (112) and to a phase adjustable clock source (108). A sampling clock signal (116) is electrically coupled from the clock source (108) to the at least one ADC (112). The at least one ADC (112) samples an electronic signal according to the sampling clock signal (116) to provide a digital representation of the electronic signal. The controller (110) samples data from the ADC (112) at different sampling points in the electronic signal and determines the edges (140) of the electronic signal and the noisy samples (142, 144) that are away from the edges (140) of the electronic signal. By finding the least noisy sample (146, 148) that is away from the edges (140) of the electronic signal the controller (110) adjusts the phase of a sampling signal clock (116) to a sampling point that is the most reliable to sample the electronic signal to provide a digital representation thereof.