Abstract: Provided are methods, systems, devices, apparatuses, and tangible non-transitory computer readable media for network topology analysis and prediction. The disclosed technology can perform operations including receiving network data including information associated with a network including a plurality of nodes respectively associated with resource availability and resource usage. Resource availability can be associated with an amount of a resource available for distribution from a portion of the plurality of nodes at an initial time interval. Further, resource usage can be associated with usage of the resource from the portion of the plurality of nodes at the initial time interval. The network topology, resource availability, and resource usage for a portion of the plurality of nodes at a time interval subsequent to the initial time interval can be determined. Furthermore, one or more predictions for the portion of the plurality of nodes can be generated based on the network data.

Abstract: A method for a systematic approach to forming experimental designs for large, complex systems after an idea for a product is formed. Critical variables for the product are determined by experts in the field, a design matrix Uk is defined, a base design matrix X is generated, Y(P)=(I?B(BTB)?1BT)[(XP)//U]A & Wynn's criterion is defined, where P is a permutation matrix, I is an identity matrix, B is a blocking matrix, BT is a transposed matrix of B and A is a matrix composed of causal map-based coefficients and wherein a design matrix Uk is created. The index k?k+1 is set and an algorithm to choose the best of random column permutation matrices P and an algorithm to choose the best column permutation matrix P that is near a previous solution and setting Uk?[XPk with rows from Uk-1 appended].

Abstract: A method of defining a toleranced process based on a nominal process, applicable to any manufacturing process wherein the output is dependent on a process having a number of input factors which are subject to variation, and have a mean and standard deviation. The method comprises the steps of: representing the variability of the response of a system to the actual distribution of at least one of said factors and parameterized by at least one parameter; performing at least one step in the manufacturing process for a given lot of wafers; evaluating actual variability and nominal variability of said components against a schedule of parameters in an array; modeling the output of the evaluation to determine the manner in which to continue processing of the lot.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors and cause shifts in the lateral placement and implant depth of TCI dopants. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. In one embodiment, a first linear or quasi-linear interpolation function is used having form: Energya=E0*(1+&bgr;*eSw/SwT), where multiplying factor &bgr; may either be a constant or a function of normalized sidewall error value, eSw/SwT. In the same embodiment, a second linear or quasi-linear interpolation function is used having form: Dosea=Dose0*(1+&agr;(L2T−L2M)/L2T), where multiplying factor &agr; is a constant or a function of normalized gate length error value, (L2T−L2M)/L2T.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.

Abstract: When Tilted Channel Implant (TCI) is performed on transistor precursor structures having an etch-defined gate length (L2M) and a trim-defined sidewall thickness (SwM), mass production deviations may cause errors between targeted values for these critical dimensions (CD's) and the correspondingly measured CD's. These deviations may respectively cause shifts in the lateral placement of TCI dopants or in the depth of implant of the TCI dopants, thereby tending to cause variation in final device characteristics. Countering adjustments to TCI dosage and TCI energy are automatically made in accordance with the invention. These countering adjustments in the TCI process enable expansion of tolerance ranges in pre-TCI production steps, thereby increase manufacturing yield.

Abstract: Identification of within-wafer and wafer-to-wafer variations in yield induced by processing steps in a multi-step manufacturing process. Methods are implemented along with wafer position tracking for process control of the manufacturing process. Wafers are systematically rotated according to their position in a batch before entering a processing step. Wafer position tracking analysis of rotated wafers advantageously reveals a static pattern on each wafer regardless of position in a batch. Alternatively, data reduction methods provide a compact representation of site-specific yield data. The data reduction methods use multidimensional scaling to determine distance factor scores and angle factor scores. The distance factor scores track changes in pattern on the wafers. Wafers similar in pattern regardless of rotation angle have similar distance factor scores. The angle factor scores track rotation of patterns on wafers.

Abstract: A method of defining a toleranced process based on a nominal process, applicable to any manufacturing process wherein the output is dependent on a process having a number of input factors which are subject to variation, and have a mean and standard deviation. The method comprises the steps of: representing the variability of the response of a system to the current variability of at least one of the factors and at least one tightening factor; evaluating the components against a schedule of tightening factors in an array; modeling the output of the evaluation using interpolation to determine a mathematical function defining the toleranced process; and applying at least one of the models to a fabrication system to complete the toleranced process.

Abstract: The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes.

Abstract: A design apparatus, article of manufacture, method and system are disclosed for simulating mass-produced semiconductor device behavior. Drain-to-source current values are obtained from actual semiconductor devices in response to voltage levels at the drain-to-source and gate of a semiconductor device. Semiconductor device attributes, such as channel-length doping concentration are also measured. A device simulator and process simulator are calibrated based upon the actual drain-to-source current values and measured attributes. A process simulator is run in response to simulated process parameters to obtain a plurality of simulated mass-produced semiconductor devices having varying semiconductor attributes. A device simulator is then run using the plurality of simulated mass-produced devices to obtain a plurality of I/V curves based upon the plurality of simulated semiconductor devices.

Abstract: A computer is used to estimate a fabrication yield for a semiconductor product under design which includes a plurality of integrated circuit dies, each of which includes a memory cache having a predetermined redundancy scheme in the form of redundant rows and/or columns. A bitmap failure analysis of an existing semiconductor product including a plurality of integrated circuit dies having bitmap failure modes that are comparable to those of the product being designed is performed to obtain a number of failed caches. An observed repair rate is computed as a ratio of a number of the failed caches that can be repaired by the predetermined redundancy scheme to the number of failed caches. A model repair rate for the predetermined redundancy scheme which approximates the observed repair rate is computed using a multiple Poisson model including computed average numbers .lambda. of failures for the failure modes respectively. The numbers .lambda.

Abstract: A system and a method for designing, fabricating and testing multiple cell test structures validate a cell library. Each test structure includes a plurality of logic layers where outputs of a logic layer are connected only to the inputs of a succeeding logic layer. In contrast to the conventional design method, mismatches in each logic layer are increased to assure extreme conditions in the test structure. For each logic layer, the number of fan-outs of each output from the previous logic layer is specified, and the number of basic cells in each layer is based on the number of inputs of the test structure. Based on D-optimality and maximum fan-in resolution, an assignment for connecting each fan-out and each fan-in is determined. Alternatively, a design repair algorithm can be used to make such an assignment. Each output of each logic cell in the logic layer is then assigned a length using D-optimality.

Abstract: A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.

Abstract: A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the model to predict cross-reticle variance from collected data for in-scribe features, (d) using the model to decompose the variance contributions of each process parameter and identify the more prominent contributors, and (e) using the model to identify the process parameter adjustments which would provide best leverage when taken one at a time.