Abstract: A pulse generation and sensing arrangement in a microprocessor system (100) includes an input/output terminal (130) which receives an input signal or produces an output signal, an edge detector (132) which senses pulse edges in the input signal, timers (108, 110) which produce time values, registers (120, 124, 126) which hold time values produced by the timers corresponding to edges detected by the edge detector or which hold values corresponding to pulse edges to be generated, comparators which compare the values held in the registers with time values produced by the timers, and a flip-flop (128) for generating a signal whose state changes in response to the comparators. The arrangement allows the generation and/or sensing of signals with short pulse widths and a wide range of duty cycles, and minimizes software overhead. A continuous PWM signal may be generated without further software involvement after initial writing of edge values.

Abstract: An analog-to-digital conversion module, QADC (1), and method minimize software involvement by providing a pause capacility. Each queue in the QADC (1) has one or more Conversion Command Words, CCWs (82), in a Conversion Command Word Table (62). Each conversion command word, CCW (82), has a Pause bit which can be used to create multiple sub-queues of A/D conversions without requiring the use of interrupts. The Pause bit can be used to place a queue in a pause state. When a queue enters a pause state, the scanning of CCWs (82) is stopped. The queue must then receive a trigger in order for the scanning of CCWs (82) to continue again.

Abstract: An analog-to-digital conversion module and method minimize software involvement by providing a programmable control table comprising a plurality of conversion command words (CCW's). Each CCW designates conversion parameters such as channel and reference selection, input sample time, and re-sample inhibit for one conversion operation, upon conclusion of which a digital value is stored in a corresponding result table. A set of CCW's defines one or more conversion sequences. Upon conclusion of each sequence, an interrupt can be issued and the result table may be read by an associated device, such as a CPU. If desired, the CCW sequence may be dynamically altered during operation of the conversion system.

Abstract: An analog-to-digital conversion system module comprises a pin-limited A/D converter integrated circuit (I.C.) to which at least one multiplexer I.C. may be coupled and sampled.In one embodiment, host system software involvement is minimized by providing a sequence of sample commands, implemented by a channel sequencer or a programmable control table comprising a plurality of conversion command words (CCW's). A set of CCW's defines a conversion sequence which may be initiated and performed with minimal host system software involvement, upon conclusion of which a result table storing the converted digital values may be read by an associated device, such as a CPU.In one embodiment, some I/O pins of the A/D converter I.C. function either as analog inputs or address outputs to the external multiplexer, while other analog input pins alternatively function as single input channels or as combined channels from one or more external multiplexers.

Abstract: An analog-to-digital conversion system module and method provides programmable times for sampling analog input signals. Software involvement is minimized by providing a command word which includes information specifying a sample time. The command word may be stored in a register or memory table. The command word or words may specify the conversion time per analog input channel or group of channels, and per conversion or conversion sequence. In one embodiment a control table comprises a plurality of conversion command words (CCW's). Each CCW designates conversion parameters including the input sample time.

Abstract: There is provided a microprocessor interface circuitry which allows single peripheral and memory devices to be used with at least two different types of microprocessors. The interface includes a latch which latches the state of a control signal provided to the peripheral/memory device by the microprocessor. The control signal that is latched serves a somewhat different function when eminating from each of the at least two different microprocessors, and as such has different logic states. Logic circuitry is controlled by the latch to take at least one other control signal and generate the internal control signals used by the peripheral/memory device.