Patents by Inventor William D. Oliver
William D. Oliver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11695417Abstract: A closed-loop feedback system and method of active noise cancellation to maintain a desired operating frequency of a qubit during a quantum computation, even when that frequency is relatively sensitive to flux noise. A series of Ramsey experiments is performed on the qubit to estimate an offset between its actual and desired operating frequencies, and the error is accumulated. After the probing is complete, the accumulated error is supplied to an arbitrary waveform generator that produces a magnetic flux that is coupled to the qubit, thereby tuning the qubit and actively controlling its operating frequency. Having corrected the operating frequency of the qubit and extended its coherence time, the quantum state of the qubit is allowed to evolve according to the computation.Type: GrantFiled: February 25, 2022Date of Patent: July 4, 2023Assignee: Massachusetts Institute of TechnologyInventors: Roni Winik, Antti Pekka Vepsalainen, Simon Gustavsson, William D. Oliver
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Patent number: 11615336Abstract: A quantum circuit called a “qumon” is provided to cancel unwanted ZZ interaction in a superconducting qubit architecture. The qumon qubit has a high coherence, and a positive anharmonicity that may be tuned to cancel the negative anharmonicity in a coupled qubit, such as a transmon qubit. The qumon has three parallel branches, in which are a shunt capacitor; a Josephson junction having weighted energy level and capacitance; and several Josephson junctions in series. The weight is chosen to provide the desired anharmonicity, and the transverse flux noise and transverse charge noise each decrease in proportion to the number of the Josephson junctions in series. Because unwanted ZZ interactions are canceled, qumon qubits and transmon qubits may be capacitively coupled in an alternating pattern to provide a surface code in which these interactions are canceled in an extensible way.Type: GrantFiled: March 1, 2021Date of Patent: March 28, 2023Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Simon Gustavsson, Roni Winik, Catherine Leroux, Agustin Di Paolo, Alexandre Blais
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Patent number: 11379749Abstract: According to some embodiments, a method can identify and discriminate contributions from one or more noise sources using the multi-level structure of a quantum system with three or more levels. The method can include: preparing the quantum system in a predetermined state; applying one or more control signals to the quantum system; measuring values of one or more observables of the quantum system that quantify the quantum system's response to the noise sources and the one or more applied control signals; extracting noise spectra information associated with the noise sources from the measured values; and identifying contributions from the one or more noise sources based on the noise spectra information.Type: GrantFiled: March 5, 2020Date of Patent: July 5, 2022Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Youngku Sung, Antti Pekka Vepsalainen, Jochen Braumueller, Simon Gustavsson
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Patent number: 11342493Abstract: A superconducting qubit is manufactured by stacking up atomically-thin, crystalline monolayers to form a heterostructure held together by van der Waals forces. Two sheets of superconducting material are separated by a third, thin sheet of dielectric to provide both a parallel plate shunting capacitor and a Josephson tunneling barrier. The superconducting material may be a transition metal dichalcogenide (TMD), such as niobium disilicate, and the dielectric may be hexagonal boron nitride. The qubit is etched, or material otherwise removed, to form a magnetic flux loop for tuning. The heterostructure may be protected by adhering additional layers of the dielectric or other insulator on its top and bottom. For readout, the qubit may be coupled to an external resonator, or the resonator may be integral with one of the sheets of superconducting material.Type: GrantFiled: November 30, 2020Date of Patent: May 24, 2022Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Simon Gustavsson, I-Jan Wang
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Publication number: 20210343923Abstract: A superconducting qubit is manufactured by stacking up atomically-thin, crystalline monolayers to form a heterostructure held together by van der Waals forces. Two sheets of superconducting material are separated by a third, thin sheet of dielectric to provide both a parallel plate shunting capacitor and a Josephson tunneling barrier. The superconducting material may be a transition metal dichalcogenide (TMD), such as niobium disilicate, and the dielectric may be hexagonal boron nitride. The qubit is etched, or material otherwise removed, to form a magnetic flux loop for tuning. The heterostructure may be protected by adhering additional layers of the dielectric or other insulator on its top and bottom. For readout, the qubit may be coupled to an external resonator, or the resonator may be integral with one of the sheets of superconducting material.Type: ApplicationFiled: November 30, 2020Publication date: November 4, 2021Inventors: William D. OLIVER, Simon GUSTAVSSON, I-Jan WANG
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Publication number: 20210279624Abstract: According to some embodiments, a method can identify and discriminate contributions from one or more noise sources using the multi-level structure of a quantum system with three or more levels. The method can include: preparing the quantum system in a predetermined state; applying one or more control signals to the quantum system; measuring values of one or more observables of the quantum system that quantify the quantum system's response to the noise sources and the one or more applied control signals; extracting noise spectra information associated with the noise sources from the measured values; and identifying contributions from the one or more noise sources based on the noise spectra information.Type: ApplicationFiled: March 5, 2020Publication date: September 9, 2021Inventors: William D. Oliver, Youngku Sung, Antti Pekka Vepsalainen, Jochen Braumueller, Simon Gustavsson
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Publication number: 20210272008Abstract: A quantum circuit called a “qumon” is provided to cancel unwanted ZZ interaction in a superconducting qubit architecture. The qumon qubit has a high coherence, and a positive anharmonicity that may be tuned to cancel the negative anharmonicity in a coupled qubit, such as a transmon qubit. The qumon has three parallel branches, in which are a shunt capacitor; a Josephson junction having weighted energy level and capacitance; and several Josephson junctions in series. The weight is chosen to provide the desired anharmonicity, and the transverse flux noise and transverse charge noise each decrease in proportion to the number of the Josephson junctions in series. Because unwanted ZZ interactions are canceled, qumon qubits and transmon qubits may be capacitively coupled in an alternating pattern to provide a surface code in which these interactions are canceled in an extensible way.Type: ApplicationFiled: March 1, 2021Publication date: September 2, 2021Inventors: William D. OLIVER, Simon GUSTAVSSON, Roni WINIK, Catherine LEROUX, Agustin DI PAOLO, Alexandre BLAIS
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Publication number: 20210150402Abstract: Techniques for machine learning assisted qubit state readout are disclosed. A system a set of training data that describes states of multiple qubits, and trains a neural network to determine qubit states based on the set of training data. The system obtains one or more unlabeled qubit signals, and determines one or more states corresponding to the unlabeled qubit signal(s), using the neural network. The unlabeled qubit signal(s) may include one or more multiplexed qubit signals, and the state(s) corresponding to the unlabeled qubit signal(s) may include one or more multi-qubit states based on the multiplexed qubit signal(s).Type: ApplicationFiled: September 18, 2020Publication date: May 20, 2021Inventors: Benjamin Lienhard, William D. Oliver, Simon Gustavsson, Antti Pekka Vepsalainen, Terry Philip Orlando, Luke Colin Gene Govia, Hari Kiran Krovi, Thomas Ohki
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Patent number: 10658424Abstract: A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.Type: GrantFiled: July 21, 2016Date of Patent: May 19, 2020Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: William D. Oliver, Rabindra N. Das, David J. Hover, Danna Rosenberg, Xhovalin Miloshi, Vladimir Bolkhovsky, Jonilyn L. Yoder, Corey W. Stull, Mark A. Gouker
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Patent number: 10396269Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.Type: GrantFiled: November 3, 2016Date of Patent: August 27, 2019Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Patent number: 10199553Abstract: Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).Type: GrantFiled: November 3, 2016Date of Patent: February 5, 2019Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Patent number: 10134972Abstract: A cryogenic quantum bit package with multiple qubit circuits facilitates inter-qubit signal propagation using a multi-chip module (MCM). Multiple qubits are grouped within the package into one or more qubit integrated circuits (ICs). The qubit ICs themselves are electrically coupled to each other via a structure including a superconducting MCM and superconducting interconnects. Coupling of quantum electrical signals between a qubit and other qubits, a substrate, or the MCM uses a coupler circuit, such as a Josephson junction, capacitor, inductor, or resonator.Type: GrantFiled: November 3, 2016Date of Patent: November 20, 2018Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Patent number: 10121754Abstract: A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.Type: GrantFiled: November 3, 2016Date of Patent: November 6, 2018Assignee: Massachusetts Institute of TechnologyInventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Publication number: 20180247974Abstract: A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called “device”) is provided as a substantially high quality factor, low loss superconducting device.Type: ApplicationFiled: July 21, 2016Publication date: August 30, 2018Inventors: William D. Oliver, Rabindra N. Das, David J. Hover, Danna Rosenberg, Xhovalin Miloshi, Vladimir Bolkhovsky, Jonilyn L. Yoder, Corey W. Stull, Mark A. Gouker
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Publication number: 20180013052Abstract: Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).Type: ApplicationFiled: November 3, 2016Publication date: January 11, 2018Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Publication number: 20180012932Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.Type: ApplicationFiled: November 3, 2016Publication date: January 11, 2018Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Publication number: 20170133336Abstract: A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.Type: ApplicationFiled: November 3, 2016Publication date: May 11, 2017Inventors: William D. Oliver, Andrew J. Kerman, Rabindra N. Das, Donna-Ruth W. Yost, Danna Rosenberg, Mark A. Gouker
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Patent number: 7912656Abstract: A system and method for providing amplitude spectroscopy is provided. Generally, the system contains a generator for providing a waveform for analysis of a multilevel quantum system, wherein the generator has the capability of changing amplitude of the waveform provided and driving the multilevel quantum system at a fixed frequency while sweeping amplitude. A detector is also provided for reading population in different energy states of the multilevel quantum system, wherein the detector plots an amplitude spectroscopy response of the multilevel quantum system. A memory and processor are provided within the system where the processor is configured by the memory to perform the step of plotting an energy-level diagram of the multilevel quantum system from the amplitude spectroscopy plot of the multilevel quantum system.Type: GrantFiled: September 3, 2009Date of Patent: March 22, 2011Assignee: Massachusetts Institute of TechnologyInventors: David M. Berns, Mark S. Rudner, Sergio O. Valenzuela, William D. Oliver, Leonid S. Levitov, Terry P. Orlando
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Publication number: 20100109638Abstract: A system and method for providing amplitude spectroscopy is provided. Generally, the system contains a generator for providing a waveform for analysis of a multilevel quantum system, wherein the generator has the capability of changing amplitude of the waveform provided and driving the multilevel quantum system at a fixed frequency while sweeping amplitude. A detector is also provided for reading population in different energy states of the multilevel quantum system, wherein the detector plots an amplitude spectroscopy response of the multilevel quantum system. A memory and processor are provided within the system where the processor is configured by the memory to perform the step of plotting an energy-level diagram of the multilevel quantum system from the amplitude spectroscopy plot of the multilevel quantum system.Type: ApplicationFiled: September 3, 2009Publication date: May 6, 2010Applicant: Massachusetts Institute of TechnologyInventors: David M. Berns, Mark S. Rudner, Sergio Valenzuela, William D. Oliver, Leonid S. Levitov, Terry P. Orlanda
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Patent number: 7093856Abstract: A truck tank to be carried in the bed of a pickup truck equipped with a bed-mounted hitch. The tank is profiled to fit within the wheel wells of the truck bed and to have either an arched recess formed in the bottom to accommodate the hitch when the tank is lifted into the bed or alternatively, an arched groove extending from the arched recess to the side of the tank so as to permit the tank to be slid into the truck bed.Type: GrantFiled: March 13, 2003Date of Patent: August 22, 2006Assignees: Flexahopper Plastics Ltd.Inventors: J. W. (Bill) Spenceley, William D. Oliver