Patents by Inventor William D. Tandy
William D. Tandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9709793Abstract: A deployable structure having a plurality of panel elements is provided. Adjacent panel elements are connected to one another by hinges. The hinges allow the panel elements to be placed in a stowed or folded configuration, in which adjacent pairs of panel elements are folded against one another to provide a relatively compact assembly. Biasing members can be provided to transition the deployable structure from the stowed configuration to a deployed configuration. When in the deployed configuration, the relative positions of the panel elements of the deployable structure are maintained, at least in part, by locating interface assemblies. The deployable structure may have a generally annular configuration when deployed.Type: GrantFiled: December 31, 2014Date of Patent: July 18, 2017Assignee: Ball Aerospace & Technologies Corp.Inventors: Aaron J. Seltzer, David M Waller, Lawrence J. Campbell, Ryan T. Thompson, Dustin S. Putnam, William D. Tandy
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Patent number: 7344921Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.Type: GrantFiled: February 21, 2006Date of Patent: March 18, 2008Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Matt E. Schwab, Cary J. Baerlocher
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Patent number: 7265453Abstract: A semiconductor component includes a leadframe, a die, upper and lower body segments encapsulating the die, and dummy segments on the leadframe. The dummy segments are configured to vent trapped air in a molding compound during molding of the body segments, such that corners of the body segments do not include the trapped air.Type: GrantFiled: September 24, 2004Date of Patent: September 4, 2007Assignee: Micron Technology, Inc.Inventors: Steven L. James, Lori Tandy, legal representative, William D. Tandy, deceased
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Patent number: 7238543Abstract: A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: GrantFiled: November 18, 2005Date of Patent: July 3, 2007Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Bret K. Street
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Patent number: 7186589Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.Type: GrantFiled: September 24, 2004Date of Patent: March 6, 2007Assignee: Micron Technology, Inc.Inventors: Steven L. James, William D. Tandy, deceased, Lori Tandy, legal representative
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Patent number: 7094618Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: GrantFiled: February 13, 2004Date of Patent: August 22, 2006Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Bret K. Street
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Patent number: 7095097Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.Type: GrantFiled: August 31, 2004Date of Patent: August 22, 2006Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Matt E. Schwab, Cary J. Baerlocher
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Patent number: 6969918Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.Type: GrantFiled: August 30, 2001Date of Patent: November 29, 2005Assignee: Micron Technology, Inc.Inventors: Steven L. James, Lori Tandy, legal representative, William D. Tandy, deceased
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Patent number: 6887740Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.Type: GrantFiled: April 10, 2003Date of Patent: May 3, 2005Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Matt E. Schwab, Cary J. Baerlocher
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Publication number: 20040161876Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including back grinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: ApplicationFiled: February 13, 2004Publication date: August 19, 2004Inventors: William D. Tandy, Bret K. Street
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Patent number: 6734032Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: GrantFiled: August 23, 2002Date of Patent: May 11, 2004Assignee: Micron Technology, Inc.Inventors: William D Tandy, Bret K. Street
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Patent number: 6692978Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.Type: GrantFiled: March 6, 2002Date of Patent: February 17, 2004Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Bret K. Street
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Publication number: 20030201547Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.Type: ApplicationFiled: April 10, 2003Publication date: October 30, 2003Applicant: Micron Technology, Inc.Inventors: William D. Tandy, Matt E. Schwab, Cary J. Baerlocher
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Patent number: 6577018Abstract: An integrated circuit device includes a semiconductor component coupled with a lead frame, and an integrated circuit package encompassing at least a portion of the semiconductor component. The package has a first surface and a second surface, and side surfaces, where the first surface is opposite the second surface. A parting line of the integrated circuit package is offset toward the second surface of the package, where the first surface optionally comprises the bottom surface of the package. The first surface of the package has one or more recessed areas.Type: GrantFiled: August 25, 2000Date of Patent: June 10, 2003Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Matt E. Schwab, Cary J. Baerlocher
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Patent number: 6524881Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogeneous surface for marking subsequent to exposure to electro-magnetic radiation.Type: GrantFiled: August 25, 2000Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventors: William D. Tandy, Bret K. Street
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Publication number: 20030003688Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: ApplicationFiled: August 23, 2002Publication date: January 2, 2003Inventors: William D. Tandy, Bret K. Street
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Publication number: 20020098608Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.Type: ApplicationFiled: March 6, 2002Publication date: July 25, 2002Inventors: William D. Tandy, Bret K. Street
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Publication number: 20020096491Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multi-level laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electro-magnetic radiation.Type: ApplicationFiled: March 6, 2002Publication date: July 25, 2002Inventors: William D. Tandy, Bret K. Street