Abstract: A scheme for bounding latency of transmissions for QoS in network stations operating in shared medium access network. The length of segment burst transmissions are limited by allowing the segment burst transmission of a given priority to be interrupted by higher priority traffic. Restrictions are placed on frame length for transmissions of all priority levels or, alternatively, at all but the highest of the priority levels.

Abstract: A CSMA Media Access Control (MAC) scheme for supporting both centralized and distributed shared medium access control in a CSMA network. A master device exchanges connection control messages with a slave during using contention-oriented access to establish a connection and a session of periodic contention-free intervals. Once the session is established, the contention-free intervals alternate with contention-oriented intervals according to the timing parameters specified by the connection control messages.

Abstract: A method of operating in a network in which stations communicate over a shared medium is described. The method provides regularly repeated contention free intervals, CSMA communication during times outside the contention free intervals, and distributed control over the initiation and makeup of the contention free intervals to a plurality of stations so that any of the plurality of stations can independently initiate transmission within the contention free interval.

Abstract: A transmit process that limits the time during which a reduced network bandwidth exists between two powerline nodes because a receiving node fails to respond to frame transmission attempts by a transmitting node is described. The transmit process restricts the number of retries that occur in a lower date rate transmission mode and, for a predetermined time period to follow, drops all subsequent frames destined for the non-responding node.

Abstract: Media Access Control (MAC) layer transmit and receive buffering with multi-level prioritization. The receive buffering allocates receive buffers for receiving frame data from a PHY interface in priority order using both a static and dynamic buffer allocation, and delivers completed buffers queued in a multi-level priority queue to a host interface highest priority first. The transmit buffering delivers completed buffers queued in a multi-level priority queue to the PHY interface in priority order. When the multi-level priority queue contains a buffer that is higher priority than one being prepared for transmit, a priority-based interruption causes the transmit processing of the buffer to be suspended at its current state with the higher priority buffer taking its place. Upon completion of the higher priority buffer, the suspended buffer is resumed at its current state.

Abstract: In a powerline network, a power line node device coupled to a host bridge application detects a “jam packet” in response to an attempt to pass a frame to the host bridge application. The powerline node device uses internal logic to override a conventional ARQ response to this and subsequent frames, in particular, when such frames are of the type for which a response is expected, with an automatic FAIL response for a predetermined time interval.

Abstract: The invention greatly reduces common bus contention by allowing the semaphore test bit and set operations to be performed on each CPU's local bus. The semaphore lock bits are stored locally in high speed SRAM on each CPU, and coherency of the lock bits is maintained through a bus monitoring logic circuit on each CPU. A CPU wishing to take possession of a semaphore performs a local read of its semaphore memory, and spins locally until the lock bit is reset at which time it performs a local write to set the bit. When the semaphore lock bit is written, it will be updated locally, and at the same time the write operation will be sent out over the common bus. The bus monitoring logic on every other CPU will recognize the write operation and simultaneously update the corresponding lock bit in each local semaphore memory. This ability to read spin locally relieves the common bus from the great amount of traffic that occurs in typical systems that maintain the semaphore lock bits in common global memory.

Abstract: The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.

Abstract: In a multiprocessor system with a common bus and a central arbitration controller, which samples the request status of every system agent, the arbitration controller grants bus accesses based on an arbitration scheme consisting of two rotating queues with a fixed priority between the queues.