Abstract: A Boundary-Scan cell (12') for facilitating testing of an electronic device (10), includes a system flip-flop (30') interposed between an output buffer (18) of the device and an internal logic block (14) which drives the buffer. The system flip-flop has asynchronous clear and preset capability which allows the flip-flop to be cleared or preset as necessary so that its output bit reflects a bit previously latched in the Boundary-Scan cell during testing. During non-testing intervals, the preset and clear capability of the system flip-flop (30') is disabled to allow the flip-flop to pass a bit between the internal logic of the device and the output buffer without undue propagation delays.

Abstract: A memory array using nonvolatile memory elements. Preferably multi-dielectric transistors are used to provide nonvolatile information storage. Good write speed is attained by providing a relatively low barrier to carrier injection. To compensate for the resulting low storage time, periodic refresh logic is provided, so that all cells in the array are refreshed at a given clock period, e.g. one second. To compensate for the changing characteristics of the nonvolatile transistors during their storage lifetime, a reference voltage generator is provided which consists of two nonvolatile memory cells programmed in opposite states, together with a resistive network for averaging their output.