Patents by Inventor William E. Sablinski
William E. Sablinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7932342Abstract: A method to reduce liquid polymer macromolecule mobility through forming a polymer blend system is provided. More particularly, a small amount of polymer crosslinker is added to a liquid polymer matrix to prevent intermolecular movement. The crosslinker functions as cages to block linear or branched linear macromolecules and prevent them from sliding into each other.Type: GrantFiled: January 16, 2008Date of Patent: April 26, 2011Assignee: International Business Machines CorporationInventors: Steven E Molis, Charles L Reynolds, William E Sablinski, Jiali Wu
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Patent number: 7767575Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: GrantFiled: January 2, 2009Date of Patent: August 3, 2010Assignee: Tessera Intellectual Properties, Inc.Inventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Publication number: 20090182161Abstract: A method to reduce liquid polymer macromolecule mobility through forming a polymer blend system is provided. More particularly, a small amount of polymer crosslinker is added to a liquid polymer matrix to prevent intermolecular movement. The crosslinker functions as cages to block linear or branched linear macromolecules and prevent them from sliding into each other.Type: ApplicationFiled: January 16, 2008Publication date: July 16, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven E. MOLIS, Charles L. REYNOLDS, William E. SABLINSKI, Jiali WU
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Publication number: 20090163019Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.Type: ApplicationFiled: January 2, 2009Publication date: June 25, 2009Applicant: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 7473997Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: September 12, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 6995084Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: GrantFiled: March 17, 2004Date of Patent: February 7, 2006Assignee: International Business Machines CorporationInventors: Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski, Julie C. Biggs, David E. Eichstadt, Jonathan H. Griffith
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Patent number: 6827505Abstract: An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.Type: GrantFiled: December 16, 2002Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Subhash L. Shinde, L. Wynn Herron, Mario J. Interrante, How T. Lin, Steven P. Ostrander, Sudipta K. Ray, William E. Sablinski, Hilton Toy
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Publication number: 20040114884Abstract: An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Subhash L. Shinde, L. Wynn Herron, Mario J. Interrante, How T. Lin, Steven P. Ostrander, Sudipta K. Ray, William E. Sablinski, Hilton Toy
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Patent number: 6574859Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by means of a screening mask. Interconnect structures are then bonded to the I/O pad.Type: GrantFiled: February 16, 2001Date of Patent: June 10, 2003Assignee: International Business Machines CorporationInventors: Shaji Farooq, Mario J. Interrante, Sudipta K. Ray, William E. Sablinski
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Patent number: 6518674Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.Type: GrantFiled: March 13, 2001Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Mario J. Interrante, Thomas E. Lombardi, Frank L. Pompeo, William E. Sablinski
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Patent number: 6429388Abstract: The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.Type: GrantFiled: May 3, 2000Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Mario J. Interrante, Brenda Peterson, Sudipta K. Ray, William E. Sablinski, Amit K. Sarkhel
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Patent number: 6303400Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.Type: GrantFiled: September 23, 1999Date of Patent: October 16, 2001Assignee: International Business Machines CorporationInventors: Mario J. Interrante, Thomas E. Lombardi, Frank L. Pompeo, William E. Sablinski
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Patent number: 6283359Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.Type: GrantFiled: August 23, 2000Date of Patent: September 4, 2001Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Mark G. Courtney, Shaji Farooq, Mario J. Interrante, Raymond A. Jackson, Gregory B. Martin, Sudipta K. Ray, William E. Sablinski, Kathleen A. Stalter
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Patent number: 6278184Abstract: A solder preform is provided for forming interconnections between multilayer ceramic substrates comprising an upper layer and lower layer of solder separated by an intermediate layer of a material which is wettable by solder and which does not melt at the temperatures used to reflow the solder and form the connections. The solder preform is used to join the substrates and is particularly useful to simultaneously electrically interconnect the substrates and to form a hermetic seal between the substrates being joined.Type: GrantFiled: September 22, 1999Date of Patent: August 21, 2001Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Patrick A. Coico, Mark G. Courtney, Lewis S. Goldmann, Raymond A. Jackson, William E. Sablinski, Kathleen A. Stalter, Hilton T. Toy, Li Wang
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Publication number: 20010008778Abstract: A temporary attach article of a first component to a second component which includes a first component having a first volume of a fusible material; a second component having a second volume of fusible material; and the first and second components being joined together through the first and second volumes of fusible material, wherein the first volume of fusible material has a melting point higher than a melting point of the second volume of fusible material so that the first and second components may be joined together without melting of the first volume of fusible material and wherein the second volume of fusible material is 5 to 20% of the first volume of fusible material. Also disclosed is a method for temporary attach of devices to an electronic substrate.Type: ApplicationFiled: March 13, 2001Publication date: July 19, 2001Applicant: International Business Machines CorporationInventors: Mario J. Interrante, Thomas E. Lombardi, Frank L. Pompeo, William E. Sablinski
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Patent number: 6253986Abstract: A solder preform is provided for forming interconnections between multilayer ceramic substrates comprising an upper layer and lower layer of solder separated by an intermediate layer of a material which is wettable by solder and which does not melt at the temperatures used to reflow the solder and form the connections. The solder preform is used to join the substrates and is particularly useful to simultaneously electrically interconnect the substrates and to form a hermetic seal between the substrates being joined.Type: GrantFiled: September 22, 1999Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Patrick A. Coico, Mark G. Courtney, Lewis S. Goldmann, Raymond A. Jackson, William E. Sablinski, Kathleen A. Stalter, Hilton T. Toy, Li Wang
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Publication number: 20010005314Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent ref lows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure.Type: ApplicationFiled: February 16, 2001Publication date: June 28, 2001Applicant: International Business Machines Corporation.Inventors: Shaji Farooq, Mario J. Interrante, Sudipta K. Ray, William E. Sablinski
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Patent number: 6235996Abstract: An interconnection structure and methods for making and detaching the same are presented for column and ball grid array (CGA and BGA) structures by using a transient solder paste on the electronic module side of the interconnection that includes fine metal powder additives to increase the melting point of the solder bond. The metal powder additives change the composition of the solder bond such that the transient melting solder composition does not completely melt at temperatures below +230° C. and detach from the electronic module during subsequent reflows. A Pb—Sn eutectic with a lower melting point is used on the opposite end of the interconnection structure. In the first method a transient melting solder paste is applied to the I/O pad of an electronic module by a screening mask. Interconnect structures are then bonded to the I/O pad.Type: GrantFiled: January 28, 1998Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Shaji Farooq, Mario J. Interrante, Sudipta K. Ray, William E. Sablinski
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Patent number: 6158644Abstract: This invention relates to a solder structure which provides enhanced fatigue life properties when used to bond substrates particularly at the second level such as BGA and CGA interconnections. The solder structure is preferably a sphere or column and has a metal layer wettable by solder and the structure is used to make solder connections in electronic components such as joining an electronic module such as a chip connected to a MLC which module is connected to a circuit board. The solder structure preferably has an overcoat of solder on the metal layer to provide a passivation coating to the metal layer to keep it clean from oxidation and corrosion and also provide a wettable surface for attachment of the solder structure to solder on the pads of the substrate being bonded.Type: GrantFiled: April 30, 1998Date of Patent: December 12, 2000Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Mark G. Courtney, Shaji Farooq, Mario J. Interrante, Raymond A. Jackson, Gregory B. Martin, Sudipta K. Ray, William E. Sablinski, Kathleen A. Stalter
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Patent number: 6070321Abstract: A solder preform is provided for forming interconnections between multilayer ceramic substrates comprising an upper layer and lower layer of solder separated by an intermediate layer of a material which is wettable by solder and which does not melt at the temperatures used to reflow the solder and form the connections. The solder preform is used to join the substrates and is particularly useful to simultaneously electrically interconnect the substrates and to form a hermetic seal between the substrates being joined.Type: GrantFiled: July 9, 1997Date of Patent: June 6, 2000Assignee: International Business Machines CorporationInventors: Peter J. Brofman, Patrick A. Coico, Mark G. Courtney, Lewis S. Goldmann, Raymond A. Jackson, William E. Sablinski, Kathleen A. Stalter, Hilton T. Toy, Li Wang