Abstract: A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the column having an index equal to the row selector is automatically reset (excepting the absent cell mentioned above) . On a read of a row, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process.

Abstract: A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A data processing system (10) has a processor (11), a display device (15), and a user input arrangement (17) which includes a pointer control device (19) such as a mouse. An edit function input is entered through the user input arrangement (17) and a target to be edited is identified in response to the edit function input. The target comprises some displayed object that is specified by proximity to a system pointer (29) at the time the edit function input is received. The edit function input defines an edit operation to be performed by the data processing system (10) on the identified target. After receiving the edit function input and responding to the input by identifying the target, the method includes determining a state of the target which indicates whether or not the edit operation is currently applied to the target. If the state of the target indicates that the edit operation is not currently applied to the target, the method includes applying the edit operation to the target.

Abstract: A method and logical apparatus for managing thread execution within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process.

Abstract: A method and multithread processor for detecting and handling the starvation of a thread. A counter associated with a first thread may be set with a pre-selected value. The counter may be updated in response to receiving a notification. The notification may indicate which, if any, group of instructions has been completed for the first and second threads. The counter may be updated in response to receiving the notification by decrementing a current value stored in the counter if the group of instructions is completed for the second thread and not for the first thread. If the value of the counter reaches a predetermined value, then a thread starvation condition may be detected for the first thread. That is, if the value of the counter reaches the predetermined value, then the first thread may be starved.

Abstract: A method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor provides a mechanism for redistributing rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper.

Abstract: A method and logical apparatus for managing resource redistribution within a simultaneous multi-threaded (SMT) processor provides a mechanism for redistributing resources between one thread during single-threaded execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, queue flushing, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process. The internal control logic then signals the resources to reallocate the resources to a single-thread if the transition is to single-threaded mode by merging partitions within the resources, or to partition themselves among the threads of the transition is to multi-threaded mode.

Abstract: A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A method of handling instructions in a load/store unit of a processor by dispatching instructions to the load/store unit, filling a portion of physical entries of a reorder queue with tags corresponding to the instructions while limiting usage of the physical entries of the reorder queue to less than a total number of physical entries, and further dispatching one or more additional instructions to the load/store unit while the filled physical entries in the reorder queue are still full, i.e., still contain tags for uncompleted instructions. The limiting of usage of the physical entries may be selectively applied. Multiple logical instruction tags are assigned in a count greater than the number of physical entries in the reorder queue. Of the multiple logical instruction tags assigned to a single one of the physical entries in the reorder queue, only the tag for the oldest instruction is allowed to execute.

Abstract: A data processing system (10) has a processor (11), a display device (15), and a user input arrangement (17) which includes a pointer control device (19) such as a mouse. An edit function input is entered through the user input arrangement (17) and a target to be edited is identified in response to the edit function input. The target comprises some displayed object that is specified by proximity to a system pointer (29) at the time the edit function input is received. The edit function input defines an edit operation to be performed by the data processing system (10) on the identified target. After receiving the edit function input and responding to the input by identifying the target, the method includes determining a state of the target which indicates whether or not the edit operation is currently applied to the target. If the state of the target indicates that the edit operation is not currently applied to the target, the method includes applying the edit operation to the target.

Abstract: A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

Abstract: A method and system for improving pre-fetch accuracy in a data processing system utilizing a pre-fetch history table is disclosed. The method compares a portion of an instruction address to an address located as an entry in a pre-fetch history table based on the status of a validity bit contained in the entry. If the validity bit is set and the addresses match, an indicator field within the entry is checked to see if it is equal to or greater than a threshold level. When the indicator field is greater than the threshold level, a target operand address is pre-fetched based on stride and direction.