Abstract: An integrated circuit, in which one or more internal parameters may be automatically configured for a particular application, includes a plurality of program select pins, each being in a predetermined fixed state, and at least one configuration pin associated with a parameter to be adjusted. Jumpers on the system board to which the integrated circuit is mounted connect the mounting pad of each configuration pin with the mounting pad of a selected program select pin. Consequently, when the integrated circuit is mounted on the system board, each configuration pin receives a selected value which internal configuration circuitry detects and causes the corresponding parameter to be adjusted accordingly. Any of the program select pins may have functions in addition to the configuration function. When the system board is powered on or undergoes a reset, a processor internal to the chip scans each the configuration pin to determine its value.

Abstract: An integrated circuit, in which one or more internal parameters may be automatically configured for a particular application, includes a plurality of program select pins, each being in a predetermined fixed state, and at least one configuration pin associated with a parameter to be adjusted. Jumpers on the system board to which the integrated circuit is mounted connect the mounting pad of each configuration pin with the mounting pad of a selected program select pin. Consequently, when the integrated circuit is mounted on the system board, each configuration pin receives a selected value which internal configuration circuitry detects and causes the corresponding parameter to be adjusted accordingly. Any of the program select pins may have functions in addition to the configuration function. When the system board is powered on or undergoes a reset, a processor internal to the chip scans each the configuration pin to determine its value.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase 2 or 3 wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.

Abstract: A fast logic gate wherein the gate output assumes a first binary state when two or more of the gate inputs assume the same predetermined binary states and wherein the gate output assumes a second binary state otherwise. The delay in propagating the gate output based on a transition at a predetermined one of the gate inputs is relatively small. In a preferred application, the gate is utilized in a microprocessor ALU, more particularly, the portion of each adder bit which generates the carry output, and the predetermined gate input is the carry input of the adder bit. The microprocessor can therefore execute instructions which involve addition or subtraction operations, such as relatively addressing instructions, much more quickily.