Patents by Inventor William Freelove

William Freelove has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11199895
    Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Kam-shing Leung, James Hermerding, II, Muhammad Abozaed, Gilad Olswang, Moran Peri, Ido Karavany, William Freelove, Sudheer Nair, Tahi Hollander, Avishai Wagner
  • Publication number: 20190129498
    Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Patrick Kam-shing Leung, James Hermerding, II, Muhammad Abozaed, Gilad Olswang, Moran Peri, Ido Karavany, William Freelove, Sudheer Nair, Tahi Hollander, Avishai Wagner
  • Publication number: 20190041950
    Abstract: In one embodiment, a processor includes one or more cores including a cache memory hierarchy; a performance monitor coupled to the one or more cores, the performance monitor to monitor performance of the one or more cores, the performance monitor to calculate pipeline cost metadata based at least in part on count information associated with the cache memory hierarchy; and a power controller coupled to the performance monitor, the power controller to receive the pipeline cost metadata and determine a low power state for the one or more cores to enter based at least in part on the pipeline cost metadata. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 7, 2019
    Inventors: Michael W. Chynoweth, Rajshree Chabukswar, Eliezer Weissmann, Jason W. Brandt, Alexander Gendler, Ahmad Yasin, Patrick Konsor, Sneha Gohad, William Freelove