Abstract: Gate oxide surface irregularities, such as surface roughness, are reduced by treatment with an oxygen-containing plasma. Embodiments include forming a gate oxide layer and then treating the formed gate oxide layer with an oxygen plasma to repair weak spots and fill in pin holes and surface irregularities, thereby reducing gate/gate oxide interface roughness.

Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

Abstract: A semiconductor device and a process for fabricating the device, including, in one embodiment, a silicon substrate; a first interfacial barrier layer on the silicon substrate, in which the first interfacial barrier layer may include aluminum oxide, silicon nitride, silicon oxynitride or a mixture thereof; and a layer of a high-K dielectric material. The device may further include a second interfacial barrier layer on the high-K dielectric material layer, and may further include a polysilicon or polysilicon-germanium gate electrode formed on the second interfacial barrier layer.

Abstract: A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate is achieved utilizing a disposable gate process and retrograde doping of the backgate.

Abstract: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: The invention provides an integrated circuit fabricated on a semiconductor substrate. The integrated circuit comprises a first field effect transistor and a second field effect transistor. The first field effect transistor comprises a first polysilicon gate positioned above a first channel region of the substrate and isolated from the first channel region by a first dielectric layer extending the entire length of the first polysilicon gate. The first dielectric layer comprises a first dielectric material with a first dielectric constant. The second field effect transistor comprises a second polysilicon gate positioned above a second channel region on the substrate and isolated from the second channel region by a second dielectric layer extending the entire length of the second polysilicon gate. The second dielectric layer comprises a second dielectric material with a second dielectric constant.

Abstract: A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.

Abstract: A method for forming a multi-layered substrate. The method includes forming a compliant layer on a face of a first substrate (10). Joining the compliant layer against a face of a second substrate (20), where the compliant layer forms around a surface non-uniformity on the second substrate face.

Abstract: An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The active layer includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having the same P or N doping type as a doping type of a body region.

Abstract: A method for forming a multi-layered substrate. The method includes forming a compliant layer on a face of a first substrate (10). Joining the compliant layer against a face of a second substrate (20), where the compliant layer forms around a surface non-uniformity on the second substrate face.

Abstract: A method of forming substrates. The method includes providing a donor substrate; and forming a cleave layer comprising a cleave plane on the donor substrate. The cleave plane extends from a periphery of the donor substrate through a center region of the substrate. The method also includes forming a device layer on the cleave layer. The method also includes selectively introducing a plurality of particles along the periphery of the cleave plane to form a higher concentration region at the periphery and a lower concentration region in the center region. Selected energy is provided to the donor substrate to initiate a cleaving action at the higher concentration region at the periphery of the cleave plane to cleave the device layer at the cleave plane.

Abstract: According to the invention, a method and circuit for measuring a transient of a MOFSET device under measurement of an SOI is provided. The device under measurement is connected from its drain to a measuring circuit having a trip point switching circuit. A supply voltage is applied to the drain through a capacitor connected to ground. When a high to low voltage pulse is applied to the source of the device, the threshold trip point can be determined whereby the dump charge through the transistor device can be determined.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: An ion implantation apparatus and method. The apparatus has a vacuum chamber and an ion beam generator to generate an ion beam in the vacuum chamber. The apparatus also has an implant wheel (10), in the vacuum chamber, having a plurality of circumferentially distributed substrate holding positions. Each of the substrate holding positions comprises a substrate holder (17), which includes an elastomer overlying the substrate holder (17) and a thermal insulating material (71) (e.g., quartz, silicon, ceramics, and other substantially non-compliant materials) overlying the elastomer (72). The present thermal insulating material increases a temperature of a substrate as it is implanted.

Abstract: A method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer.

Abstract: A method of fabricating a silicon-on-insulator (SOI) chip having an active layer with a non-uniform thickness. The method includes the steps of providing a substrate; providing a buried oxide layer (BOX) on the substrate; providing an active layer on the BOX layer, the active layer having an initially uniform thickness; dividing the active layer into at least a first and a second tile; and altering the thickness of the active layer in the area of the second tile. The method also includes forming a plurality of partially depleted semiconductor devices from the active layer in the area of a thicker of the first and the second tiles and forming a plurality of fully depleted semiconductor devices from the active layer in the area of a thinner of the first and the second tiles.