Patents by Inventor William G. Rivard

William G. Rivard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150229819
    Abstract: A system, method, and computer program product for generating an image set is disclosed. The method comprises receiving a shutter release command, generating a first image of a photographic scene based on a first set of sampling parameters in response to the shutter release command, storing the first image within the image set, generating a second image of the photographic scene based on a second set of sampling parameters in response to the shutter release command, and storing the second image within the image set. The first set of sampling parameters specifies a first strobe intensity, and the second set of sampling parameters specifies a second strobe intensity. A strobe unit is configured to generate strobe illumination within the photographic scene according to the first strobe intensity or the second strobe intensity.
    Type: Application
    Filed: February 12, 2014
    Publication date: August 13, 2015
    Inventors: William G. Rivard, Adam B. Feder, Brian J. Kindle
  • Publication number: 20040078508
    Abstract: A new storage system architecture is described that satisfies the requirements of high availability and high performance. High performance is achieved by utilizing both parallel RAID data paths to disk and a split read and write cache. The read cache is associated with a host interface controller and the write cache is distributed over independent multi-ported write cache controllers operating within a battery protected power domain. Disk and write cache failures are survived through disk redundancy; controller redundancy provides system level survival for system faults. The system is therefore tolerant of both component and power failure, including combined component and power failure.
    Type: Application
    Filed: October 2, 2003
    Publication date: April 22, 2004
    Inventor: William G. Rivard
  • Patent number: 6636227
    Abstract: A method and apparatus for grouping texture data to increase storage throughput. Texels are addressed and stored according to adjacency to enable retrieval of a plurality of texels (a cache entry) with only a single address space request. Individual texel position is then derived using a simple adjacency formula. The preferred method and apparatus are compatible with both tiled data and linear data storage formats.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: October 21, 2003
    Assignee: NVIDIA U.S. Investment Company
    Inventors: William G. Rivard, Emmett Michael Kilgariff
  • Patent number: 6300953
    Abstract: A method and apparatus for grouping texture data to increase storage throughput. Texels are addressed and stored according to adjacency to enable retrieval of a plurality of texels (a cache entry) with only a single address space request. Individual texel position is then derived using a simple adjacency formula. The preferred method and apparatus are compatible with both tiled data and linear data storage formats.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: October 9, 2001
    Assignee: nVidia
    Inventors: William G. Rivard, Emmett Michael Kilgariff
  • Patent number: 5987567
    Abstract: A system for caching texel information in a cache data store, for use in a graphics rendering system which uses interpolative sampling to compute texture color values. The system includes a texel memory storing texel information, a graphics application program for using interpolative sampling to compute dynamic texture values, a first cache data storage for a number of the most-recently-retrieved texels, a second cache data storage for a previously-retrieved adjacent line of texels, cache tag blocks for determining whether the texels needed by the graphics accelerator system are cached in either of the first or second cache data stores, and a memory request generator for retrieving texels from texel memory upon indication of a miss by the cache tag blocks.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: November 16, 1999
    Assignee: Apple Computer, Inc.
    Inventors: William G. Rivard, Stephanie L. Winner, Michael W. Kelley